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伊藤 靖朗 (Yasuaki Ito)

  • 広島大学大学院先進理工系科学研究科情報科学プログラム / 情報科学部計算機科学プログラム
  • 知的システム研究室

経歴

学歴

  • 1997年 4月 名古屋工業大学 工学部 電気情報工学科 入学
  • 2001年 3月 名古屋工業大学 工学部 電気情報工学科 計算機システムコース 卒業 学士(工学)
  • 2001年 4月 北陸先端科学技術大学院大学 情報科学研究科 情報処理学専攻 博士課程前期 入学
  • 2003年 3月 北陸先端科学技術大学院大学 情報科学研究科 情報処理学専攻 博士課程前期 修了 修士(情報科学)
  • 2004年 4月 広島大学大学院 工学研究科 複雑システム工学専攻 博士課程後期 入学
  • 2004年 9月 広島大学大学院 工学研究科 複雑システム工学専攻 博士課程後期 退学
  • 2008年10月 広島大学大学院 工学研究科 情報工学専攻 博士課程後期 入学
  • 2010年 9月 広島大学大学院 工学研究科 情報工学専攻 博士課程後期 修了 博士(工学)

職歴

  • 2003年 4月--12月 デンソーテクノ(株)
  • 2004年 9月 広島大学 COE研究員
  • 2004年10月--2006年3月 広島大学大学院工学研究科 複雑システム工学専攻 助手
  • 2006年 4月--2007年3月 広島大学大学院工学研究科 情報工学専攻 助手
  • 2007年 4月--2010年3月 広島大学大学院工学研究科 情報工学専攻 助教
  • 2010年 4月--2013年9月 広島大学大学院工学研究院 情報部門 助教(改組による名称変更)
  • 2013年10月--2016年3月 広島大学大学院工学研究院 情報部門 准教授
  • 2016年 4月--2017年3月 広島大学学術院 准教授 (大学院工学研究院 情報部門)
  • 2017年 4月--2020年3月 広島大学学術院 准教授 (大学院工学研究科 情報工学専攻 情報工学講座) (名称変更)
  • 2020年 4月--2022年9月 広島大学学術院 准教授 (大学院先進理工系科学研究科 情報科学プログラム) (改組による名称変更)
  • 2022年10月--現在 広島大学学術院 教授 (大学院先進理工系科学研究科 情報科学プログラム)
  • 2022年11月--現在 広島大学 富士通次世代コンピューティング共同研究講座 共同研究講座併任教授

研究業績

学術論文 (Journal Papers)

  1. Jiamian Huang, Yasuaki Ito and Koji Nakano, GPU-accelerated High-quality Watercolor Painting Image Generation, Concurrency and Computation: Practice and Experience, to appear. (DOI)
  2. Koji Nakano, Shunsuke Tsukiyama, Yasuaki Ito, Takashi Yazane, Junko Yano, Takumi Kato, Shiro Ozaki, Rie Mori, and Ryota Katsuki, Dual-Matrix Domain Wall: A Novel Technique for Generating Permutations by QUBO and Ising Models with Quadratic Sizes, Technologies, vol. 11, no. 5, 143, 2023. (DOI)
  3. Daisuke Takafuji, Koji Nakano, Yasuaki Ito, Akihiko Kasagi, GPU implementations of Deflate Encoding and Decoding, Concurrency and Computation: Practice and Experience, Vol. 35, No. 19, e7454, 2023. (DOI)
  4. Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano, Simple iterative trial search for the maximum independent set problem optimized for the GPUs, Concurrency and Computation: Practice and Experience, Vol. 35, No. 14, e6681, 2023. (DOI)
  5. Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano, High-throughput FPGA Implementation for Quadratic Unconstrained Binary Optimization, Concurrency and Computation: Practice and Experience, Vol. 35, No. 14, e6565, 2023. (DOI)
  6. Naoki Matsumura, Yasuaki Ito, Koji Nakano, Akihiko Kasagi, Tsuguchika Tabaru, A novel structured sparse fully connected layer in convolutional neural networks, Concurrency and Computation: Practice and Experience, Vol. 35, No. 11, e6213, 2023. (DOI)
  7. Daisuke Takafuji, Koji Nakano, Yasuaki Ito, Efficient parallel implementations to compute the diameter of a graph, Concurrency and Computation: Practice and Experience, Vol. 35, No. 11, e5963, 2023. (DOI)
  8. Ryota Yasudo, Koji Nakano, Yasuaki Ito, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano, GPU-accelerated Scalable Solver with Bit Permutated Cyclic-Min Algorithm for Quadratic Unconstrained Binary Optimization, Journal of Parallel and Distributed Computing, vol. 167, pp. 109-122, 2022. (DOI)
  9. Naoki Matsumura, Hiroki Tokura, Yuki Kuroda, Yasuaki Ito, Koji Nakano, Tile art image generation using parallel greedy algorithm on the GPU and its approximation with machine learning, Concurrency and Computation: Practice and Experience, Vol. 33, No. 12, e5623, June 2021. (DOI)
  10. Takuma Wada, Naoki Matsumura, Ryota Yasudo, Koji Nakano, Yasuaki Ito, Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA, Concurrency and Computation: Practice and Experience, Vol. 33, No. 12, e5475, June 2021. (DOI)
  11. Lucas Saad Nogueira Nunes, Jacir Luiz Bordim, Yasuaki Ito, and Koji Nakano, A Rabin-Karp Implementation for Handling Multiple Pattern-Matching on the GPU, IEICE Transactions on Information and Systems, Vol. E103-D, No, 12, pp. 2412--2420, December 2020. (DOI)
  12. Shunsuke Suita, Takahiro Nishimura, Hiroki Tokura, Koji Nakano, Yasuaki Ito, Akihiko Kasagi, Tsuguchika Tabaru, Efficient Convolution-Pooling on the GPU, Journal of Parallel and Distributed Computing, Vol. 138, pp. 222-229, April 2020. (DOI)
  13. Takahiro Nishimura, Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Accelerating the Smith-Waterman Algorithm Using the Bitwise Parallel Bulk Computation Technique on the GPU, IEICE Transactions on Information and Systems, Vol. E102-D, No. 12, pp. 2400--2408, December 2019. (DOI)
  14. Kohei Yamashita, Yasuaki Ito, Koji Nakano, Bulk execution of the dynamic programming for the optimal polygon triangulation problem on the GPU, Concurrency and Computation: Practice and Experience, Vol. 31, No. 19, e4947, September, 2019. (DOI)
  15. Hiroki Tokura, Toru Fujita, Koji Nakano, Yasuaki Ito, and Jacir L. Bordim, Almost optimal column-wise prefix-sum computation on the GPU, The Journal of Supercomputing, Vol. 74, No. 4, pp. 1510--1521, April 2018. (DOI)
  16. Toru Fujita, Koji Nakano, Yasuaki Ito, and Daisuke Takafuji, An Efficient GPU Implementation of CKY Parsing using the Bitwise Parallel Bulk Computation Technique, IEICE Transactions on Information and Systems, Vol. E100-D, No, 12, pp. 2857--2865, December 2017. (DOI)
  17. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, Adaptive loss-less data compression method optimized for GPU decompression, Concurrency and Computation: Practice and Experience, Vol. 29, No. 24, e4283, November, 2017. (DOI)
  18. Daisuke Takafuji, Koji Nakano, Yasuaki Ito, and Jacir Bordim, C2CU: a CUDA C program generator for bulk execution of a sequential algorithm, Concurrency and Computation: Practice and Experience, Vol. 29, No. 17, e4022, September 2017. (DOI)
  19. Hiroki Tokura, Takumi Honda, Yasuaki Ito, Koji Nakano, Mitsuya Nishino, Yushiro Hirota and Masami Saeki, An Efficient GPU Implementation of Bulk Computation of the Eigenvalue Problem for Many Small Real Non-symmetric Matrices, International Journal of Networking and Computing, Vol. 7, No. 2, pp. 227--247, July 2017. (DOI)
  20. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Exhaustive Verification of the Collatz Conjecture, International Journal of Networking and Computing, Vol. 7, No. 1, pp. 69--85, January 2017. (DOI)
  21. Hiroaki Koge, Takumi Honda, Toru Fujita, Yasuaki Ito, Koji Nakano, and Jacir L. Bordim, Accelerating digital halftoning using the local exhaustive search on the GPU, Concurrency and Computation: Practice and Experience, Vol. 29, No. 2, e3781, January 2017. (DOI)
  22. Toru Fujita, Koji Nakano, and Yasuaki Ito, Fast Simulation of Conway's Game of Life using Bitwise Parallel Bulk Computation on a GPU, International Journal of Foundations of Computer Science, Vol. 27, No. 08, pp. 981--1003, December 2016. (DOI)
  23. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, Fully Parallelized LZW decompression for CUDA-enabled GPUs, IEICE Transactions on Information and Systems, Vol. E99-D, No. 12, pp. 2986--2994, December 2016. (DOI)
  24. Lucas Saad Nogueira Numes, Jacir Luiz Bordim, Koji Nakano, and Yasuaki Ito, A Memory-access-efficient Implementation for Computing the Approximate String Matching Algorithm on GPUs, IEICE Transactions on Information and Systems, Vol. E99-D, No. 12, pp. 2995--3003, December 2016. (DOI)
  25. Tatsuya Kawamoto, Xin Zhou, Jacir L. Bordim, Yasuaki Ito, and Koji Nakano, An FPGA implementation for a flexible-length-arithmetic processor employing the FDFM processor core approach, IEICE Transactions on Information and Systems, Vol. E99-D, No. 12, pp. 2901--2910, December 2016. (DOI)
  26. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Bulk Execution of Multiple-length Multiplication with Warp-synchronous Programming Technique, IEICE Transactions on Information and Systems, Vol. E99-D, No. 12, pp. 3004--3012, December 2016. (DOI)
  27. Xin Zhou, Koji Nakano, Yasuaki Ito, Efficient Implementation of FDFM Approach for Euclidean Algorithms on the FPGA, International Journal of Networking and Computing, Vol. 6, No. 2, pp. 420--435, July 2016. (DOI)
  28. Yuji Takeuchi, Koji Nakano, Daisuke Takafuji, and Yasuaki Ito, A character art generator using the local exhaustive search, with GPU acceleration, International Journal of Parallel, Emergent and Distributed Systems, Vol. 31, No. 1, pp. 47--63, January 2016. (DOI)
  29. Toru Fujita, Koji Nakano, and Yasuaki Ito, Bulk execution of Euclidean algorithms on the CUDA-enabled GPU, International Journal of Networking and Computing, Vol. 6, No. 1, pp. 42--63, January 2016. (DOI)
  30. Duhu Man, Koji Nakano, Yasuaki Ito, An Optimal Implementation of the Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation on the GPU, IEICE Transactions on Information and Systems, Vol. E97-D, No.12, pp.3063--3071, December 2014. (DOI)
  31. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Offline Permutation on the CUDA-enabled GPU, IEICE Transactions on Information and Systems, Vol. E97-D, No.12, pp. 3052--3062, December 2014.(DOI)
  32. Akihiro Uchida, Yasuaki Ito and Koji Nakano, Accelerating ant colony optimisation for the travelling salesman problem on the GPU, International Journal of Parallel, Emergent and Distributed Systems, Vol. 29, No. 4, pp. 401--420, 2014. (DOI)
  33. Xin Zhou, Norihiro Tomagou, Yasuaki Ito, and Koji Nakano, Implementations of the Hough Transform on the Embedded Multicore Processors, International Journal of Networking and Computing, Vol. 4, No. 1, pp. 174--188, January 2014. (DOI)
  34. Yasuaki Ito and Koji Nakano, A GPU Implementation of Dynamic Programming for the Optimal Polygon Triangulation, IEICE Transactions on Information and Systems, Vol. E96-D, No. 12, pp. 2596--2603, December 2013. (DOI)
  35. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Offline Permutation Algorithms on the Discrete Memory Machine with Performance Evaluation on the GPU, IEICE Transactions on Information and Systems, Vol. E96-D, No. 12, pp. 2617--2625, December 2013. (DOI)
  36. Duhu Man, Kenji Uda, Yasuaki Ito and Koji Nakano, Accelerating computation of Euclidean distance map using the GPU with Efficient memory access, International Journal of Parallel, Emergent and Distributed Systems, Vol. 28, No. 5, pp. 383--406, 2013. (DOI)
  37. Yuki Ago, Yasuaki Ito, Koji Nakano, An FPGA implementation for neural networks with the FDFM processor core approach, International Journal of Parallel, Emergent and Distributed Systems, Vol. 28, No. 4, pp. 308-320, 2013. (DOI)
  38. Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito, A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with Cycles, International Journal of Networking and Computing, Vol. 2, No. 1, pp. 269--290, July 2012. (DOI)
  39. Md. Nazrul Islam Mondal, Koji Nakano and Yasuaki Ito, An Algorithm to Obtain Circuits with Synchronous RAMs, Journal of Communication and Computer, Vol. 9, No. 5, pp. 547-559, May 2012.
  40. Yasuaki Ito, Koji Nakano and Song Bo, The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption, International Journal of Networking and Computing, Vol. 2, No. 1, pp. 79--96, January 2012. (DOI)
  41. Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito, A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones, IEICE Transactions on Information and Systems, Vol. E94-D, No. 12, pp.2378--2388, December 2011. (DOI)
  42. Duhu Man, Yasuaki Ito, Koji Nakano, An Efficient Parallel Sorting Compatible with the Standard qsort, International Journal on Foundations of Computer Science, Vol. 22, No. 5, pp. 1057--1071, August 2011. (DOI)
  43. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito and Koji Nakano, Implementations of a Parallel Algorithm for Computing Euclidean Distance Map in Multicore Processors and GPUs, International Journal of Networking and Computing, Vol. 1, No. 2, pp. 260--276, July 2011. (DOI)
  44. Song Bo, Kensuke Kawakami, Koji Nakano and Yasuaki Ito, An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA, International Journal of Networking and Computing, Vol. 1, No. 2, pp. 277--289, July 2011. (DOI)
  45. Yasuaki Ito, Koji Nakano, Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs, International Journal of Networking and Computing, Vol. 1, No. 1, pp.49--62, January 2011. (DOI)
  46. Yasuaki Ito, Koji Nakano, Low-Latency Connected Component Labeling Using an FPGA, International Journal on Foundations of Computer Science, Vol. 21, No.3, pp.405--426, June 2010. (DOI)
  47. Yasuaki Ito, Koji Nakano, A New FM Screening Method to Generate Cluster-Dot Binary Images Using the Local Exhaustive Search with FPGA Acceleration, International Journal on Foundations of Computer Science, Vol. 19, No. 6, pp. 1373--1386, December 2008. (DOI)
  48. Yasuaki Ito, Koji Nakano, Youhei Yamagishi, Efficient Hardware Algorithms for N Choose K Counters Using the Bitonic Merger, International Journal on Foundations of Computer Science, Vol. 18, No.3, pp.517--528, June, 2007. (DOI)
  49. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, An Energy Efficient Leader Election Protocol for Radio Network with a Single Transceiver, IEICE Trans. on Fundamentals, Vol. E89-A, No.5 pp. 1355--1361, May 2006. (DOI)
  50. Yasuaki Ito and Koji Nakano, FM Screening by the Local Exhaustive Search with Hardware Acceleration, International Journal of Foundations of Computer Science, Vol. 16, No.1, pp.89--104, February 2005. (DOI)
  51. Jacir L Bordim, Oscar H. Ibarra, Yasuaki Ito, and Koji Nakano, Instance-Specific Solutions to Accelerate the CKY Parsing for Large Context-free Grammars, International Journal on Foundations of Computer Science, Vol 15, No.2, pp.403--416, April 2004. (DOI)
  52. Jacir L Bordim, Yasuaki Ito, Koji Nakano, Accelerating the CKY parsing using FPGAs, IEICE Transactions on Information and Systems, Vol. E86-D, No.5, pp.803--810, May 2003.

国際会議(査読あり) (International Conferences (Refereed))

  1. Satoki Tsuji, Yasuaki Ito, Koji Nakano, Akihiko Kasagi, Efficient GPU-Accelerated Bulk Evaluation of the Boys Function for Quantum Chemistry, in Proc. of International Symposium on Computing and Networking Workshops, pp. 49-58, Matsue, Shimane, November 2023. (DOI)
  2. Shunsuke Tsukiyama, Koji Nakano, Yasuaki Ito, Takashi Yazane , Junko Yano, Takumi Kato, Shiro Ozaki, Rie Mori, Ryota Katsuki, Solving the N-Queens Puzzle by a QUBO Model with Quadratic Size, in Proc. of International Symposium on Computing and Networking Workshops, pp. 49-58, Matsue, Shimane, November 2023. (DOI)
  3. Koji Nakano, Daisuke Takafuji, Yasuaki Ito, Takashi Yazane, Junko Yano, Shiro Ozaki, Ryota Katsuki, Rie Mori, Diverse Adaptive Bulk Search: a Framework for Solving QUBO Problems on Multiple GPUs, in Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 314-325, May 2023. (DOI)
  4. Koji Nakano, Yasuaki Ito, Daisuke Takafuji, Takashi Yazane, Junko Yano, Shiro Ozaki, Ryota Katsuki, Rie Mori, A benchmark QUBO problem inspired by digital halftoning based on the human visual system, in Proc. of International Symposium on Computing and Networking, pp. 56-65, Himeji, Hyogo, November 2022. (DOI)
  5. Haiya Huang, Yasuaki Ito, Koji Nakano, A Bokeh Image Generation Technique Using Machine Learning, in Proc. of International Symposium on Computing and Networking, pp. 97-103, Himeji, Hyogo, November 2022. (DOI, Outstanding Paper Award)
  6. Hao Su, Jiamian Huang, Yasuaki Ito, Koji Nakano, ConvUNeXt: A Lightweight Convolutional Neural Network for Watercolor Image Translation, in Proc. of International Symposium on Computing and Networking Workshops, pp. 127-133, Himeji, Hyogo, November 2022.
  7. Xiaotian Li, Koji Nakano, Yasuaki Ito, Daisuke Takafuji, Takashi Yazane, Junko Yano, Shiro Ozaki, Ryota Katsuki, Rie Mori, Bit Duplication Technique to Generate Hard QUBO Problems, in Proc. of International Symposium on Computing and Networking Workshops, pp. 180-184, Himeji, Hyogo, November 2022.
  8. Taiki Sasaki, Yasuaki Ito, Koji Nakano, Akihiko Kasagi, BERT-based Scientific Paper Quality Prediction, in Proc. of 31st International Conference on Artificial Neural Networks, LNCS 13532, pp. 212-223, September 2022. (DOI)
  9. Yasuaki Ito, Koji Nakano, Akihiko Kasagi, The Bonsai Hypothesis: an Efficient Network Pruning Technique, in Proc. of 18th International Conference on Artificial Intelligence Applications and Innovations, IFIP Advances in Information and Communication Technology, vol 646, pp.229-241, June 2022. (DOI)
  10. Ryota Yasudo, Koji Nakano, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane and Kenichiro Hamano, Graph-theoretic Formulation of QUBO for Scalable Local Search on GPUs, in Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 425-434, May 2022. (DOI)
  11. Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane and Kenichiro Hamano, Solving the sparse QUBO on multiple GPUs for Simulating a Quantum Annealer, in Proc. of International Symposium on Computing and Networking, pp. 19-28, Matsue, Shimane (Online), November 2021. (DOI)
  12. Daisuke Takafuji, Koji Nakano, Yasuaki Ito and Akihiko Kasagi, Acceleration of Deflate Encoding and Decoding with GPU implementations, in Proc. of International Symposium on Computing and Networking Workshops, pp. 180-186, Matsue, Shimane (Online), November 2021. (DOI)
  13. Jiamian Huang, Yasuaki Ito and Koji Nakano, A GPU Implementation of Watercolor Painting Image Generation, in Proc. of International Symposium on Computing and Networking Workshops, pp. 145-151, Matsue, Shimane (Online), November 2021. (DOI, Best Paper Award)
  14. Koji Nakano, Shotaro Aoki, Yasuaki Ito, On the Computational Power of Convolution Pooling: A Theoretical Approach for Deep Learning, in Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 656--665, May 2021. (DOI)
  15. Tomohiro Imanaga, Koji Nakano, Masaki Tao, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane and Kenichiro Hamano, Efficient GPU Implementation for Solving the Maximum Independent Set Problem, in Proc. of International Symposium on Computing and Networking, pp. 29-38, Naha, Japan (Online), November 2020. (DOI)
  16. Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano, Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA, in Proc. of International Symposium on Computing and Networking, pp. 39-48, Naha, Japan (Online), November 2020. (DOI, Best Paper Award)
  17. Ye Yuan, Yasuaki Ito, and Koji Nakano, Art Font Image Generation with Conditional Generative Adversarial Networks, in Proc. of International Symposium on Computing and Networking Workshops, pp. 151-156, Naha, Japan (Online), November 2020. (DOI, Best Paper Award)
  18. Naoya Yamamoto, Koji Nakano, Yasuaki Ito, and Daisuke Takafuji, Akihiko Kasagi, Tsuguchika Tabaru, Huffman Coding with Gap Arrays for GPU Acceleration, in Proc. of International Conference on Parallel Processing (ICPP), article no. 1, pages 11, Edmont, Canada (online), August 2020. (DOI, Best paper award)
  19. Ryota Yasudo, Koji Nakano, Yasuaki Ito, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, Yoko Inaba, Adaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs, in Proc. of International Conference on Parallel Processing (ICPP), article no. 62, pages 11, Edmont, Canada (online), August 2020. (DOI)
  20. Hiroki Kataoka, Kohei Yamashita, Yasuaki Ito, Koji Nakano, Akihiko Kasagi, Tsuguchika Tabaru, An Efficient Multicore CPU Implementation for Convolution-Pooling Computation in CNNs, in Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 548-556, May 2020. (DOI)
  21. Masaki Tao, Koji Nakano, Yasuaki Ito, Ryota Yasudo, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, Yoko Inaba, A Work-Time Optimal Parallel Exhaustive Search Algorithm for the QUBO and the Ising model, with GPU implementation, in Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 557-566, May 2020. (DOI)
  22. Masatoshi Hayashikawa, Koji Nakano, Yasuaki Ito, and Ryota Yasudo, Folded Bloom Filter for High Bandwidth Memory, with GPU implementations, in Proc. of International Symposium on Computing and Networking, pp. 18--27, Nagasaki, Japan, November 2019. (DOI)
  23. Hiroshi Kagawa, Yasuaki Ito, and Koji Nakano, Throughput-Optimal Hardware Implementation of LZW Decompression on the FPGA, in Proc. of International Symposium on Computing and Networking Workshops, pp. 78--83, Nagasaki, Japan, November 2019. (DOI)
  24. Daisuke Takafuji, Koji Nakano, Yasuaki Ito, Efficient GPU Implementations to Compute the Diameter of a Graph, in Proc. of International Symposium on Computing and Networking, pp. 102--111, Nagasaki, Japan, November 2019. (DOI)
  25. Naoki Matsumura, Yasuaki Ito, Koji Nakano, Akihiko Kasagi and Tsuguchika Tabaru, Structured Sparse Fully-Connected Layers in the CNNs and its GPU Acceleration, in Proc. of International Symposium on Computing and Networking Workshops, pp. 148--154, Nagasaki, Japan, November 2019. (DOI, Best paper award)
  26. Hisaki Yamane, Yasuaki Ito, and Koji Nakano, A Watercolor Painting Image Generation using Stroke-based Rendering, in Proc. of International Symposium on Computing and Networking Workshops, pp. 465--469, Nagasaki, Japan, November 2019. (DOI)
  27. Shunsuke Suita, Takahiro Nishimura, Hiroki Tokura, Koji Nakano, Yasuaki Ito, Akihiko Kasagi and Tsuguchika Tabaru, Efficient cuDNN-compatible Convolution-Pooling on the GPU, in Proc. of 13th International Conference of Parallel Processing and Applied Mathematics (PPAM 2019, LNCS, volume 12044), pp. 46--58, Bialystok, Poland, September 2019.
  28. Takahiro Inoue, Hiroki Tokura, Koji Nakano and Yasuaki Ito, Efficient Triangular Matrix Vector Multiplication on the GPU, in Proc. of 13th International Conference of Parallel Processing and Applied Mathematics (PPAM 2019, LNCS, volume 12043), pp. 493--504, Bialystok, Poland, September 2019. (DOI)
  29. Hironobu Kobayashi, Yasuaki Ito and Koji Nakano, Stained Glass Image Generation using Voronoi Diagram and its GPU Acceleration, in Proc. of 13th International Conference of Parallel Processing and Applied Mathematics (PPAM 2019, LNCS, volume 12043), pp. 396--407, Bialystok, Poland, September 2019.
  30. Koji Nakano, Yasuaki Ito, Jacir Bordim, FIFO-Based Hardware Sorters for High Bandwidth Memory, in Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 663-672, Rio de Janeiro, Brazil, May 2019. (DOI)
  31. Takuma Wada, Naoki Matsumura, Koji Nakano, Yasuaki Ito, Efficient Byte Stream Pattern Test using Bloom Filter with Rolling Hash Functions on the FPGA, in Proc. of International Symposium on Computing and Networking, pp. 66--75, Takayama, Japan, November 2018. (DOI, Best paper award)
  32. Lucas S. N. Nunes, Jacir L. Bordim, Yasuaki Ito, Koji Nakano, A Prefix-Sum-Based Rabin-Karp Implementation for Multiple Pattern Matching on GPGPU, in Proc. of International Symposium on Computing and Networking, pp. 139--145, Takayama, Japan, November 2018. (DOI)
  33. Naoki Matsumura, Hiroki Tokura, Yuki Kuroda, Yasuaki Ito, Koji Nakano, Tile Art Image Generation Using Conditional Generative Adversarial Networks, in Proc. of International Symposium on Computing and Networking Workshops, pp. 209--215, Takayama, Japan, November 2018. (DOI)
  34. Yutaro Emoto, Shunji Funasaka, Hiroki Tokura, Takumi Honda, Koji Nakano and Yasuaki Ito, An Optimal Parallel Algorithm for Computing the Summed Area Table on the GPU, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 763--772, Vancouver, Canada, May 2018. (DOI)
  35. Hiroki Tokura, Yuki Kuroda, Yasuaki Ito, and Koji Nakano, Parallel High-Quality Art Generation From Any Image Using A GPU, in Poster in the GPU Technology Conference (GTC 2018), San Jose, USA, March 2018.
  36. Shunji Funasaka, Koji Nakano, Yasuaki Ito, Single Kernel Soft Synchronization Technique for Task Arrays on CUDA-enabled GPUs, with Applications, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 11--20, Aomori, Japan, November 2017. (DOI)
  37. Hiroki Tokura, Yuki Kuroda, Yasuaki Ito, and Koji Nakano, A Square Pointillism Image Generation, and its GPU Acceleration, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 38--47, Aomori, Japan, November 2017. (DOI, Outstanding paper award)
  38. Takuma Wada, Shunji Funasaka, Koji Nakano and Yasuaki Ito, A Hybrid Architecture for the Approximate String Matching on an FPGA, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 48--57, Aomori, Japan, November 2017. (DOI)
  39. Kohei Yamashita, Yasuaki Ito and Koji Nakano, A GPU Implementation of Bulk Execution of the Dynamic Programming for the Optimal Polygon Triangulation, in Proc. of 12th International Conference of Parallel Processing and Applied Mathematics (PPAM 2017, LNCS 10777), pp. 314--323, Lublin, Poland, September 2017. (DOI)
  40. Hiroki Tokura, Toru Fujita, Koji Nakano and Yasuaki Ito, Almost Optimal Column-wise Prefix-sum Computation on the GPU, in Proc. of 12th International Conference of Parallel Processing and Applied Mathematics (PPAM 2017, LNCS 10778), pp. 224--233, Lublin, Poland, September 2017. (DOI)
  41. Takumi Honda, Shinnosuke Yamamoto, Hiroaki Honda, Koji Nakano, Yasuaki Ito, Simple and Fast Parallel Algorithms for the Voronoi Map and the Euclidean Distance Map, with GPU implementations, in Proc. of 46th International Conference on Parallel Processing (ICPP), pp. 362--371, Bristol, UK, August 2017. (DOI)
  42. Yi Yang, Yasuaki Ito, and Koji Nakano, Photomosaic Generation by Rearranging Subimages, with GPU Acceleration, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 942--951, Orlando, USA, May 2017. (DOI)
  43. Takahiro Nishimura, Jacir L. Bordim, Yasuaki Ito, and Koji Nakano, Accelerating the Smith-Waterman Algorithm Using Bitwise Parallel Bulk Computation Technique on GPU, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 932--941, Orlando, USA, May 2017. (DOI)
  44. Koji Nakano, Shunji Funasaka, Yasuaki Ito, A Very Fast Data Compression Method Optimized for GPU Decompression, in Poster in the GPU Technology Conference (GTC 2017), San Jose, USA, May 2017. (Selected as one of Top 20 posters)
  45. Yi Yang, Yasuaki Ito, Koji Nakano, and Jacir L. Bordim, A Photomosaic Method by Rearranging Divided Images with GPU Acceleration, in Poster in the GPU Technology Conference (GTC 2017), San Jose, USA, May 2017.
  46. Shunji Funasaka, Koji Nakano and Yasuaki Ito, Light Loss-Less Data Compression, with GPU implementation, Proc. of the 16th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 10048), pp. 281--294, Granada, Spain, December 2016. (DOI)
  47. Xin Zhou, Yasuaki Ito and Koji Nakano, An Efficient Implementation of LZW Compression in the FPGA, Proc. of the 16th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 10048), pp. 512--520, Granada, Spain, December 2016. (DOI)
  48. Ryouhei Murooka, Yasuaki Ito and Koji Nakano, Accelerating Ant Colony Optimization for the Vertex Coloring Problem on the GPU, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 469--475, Hiroshima, Japan, November 2016. (DOI)
  49. Lucas Saad, Jacir Bordim, Yasuaki Ito and Koji Nakano, A Memory-Access-Efficient Implementation of the Approximate String Matching Algorithm on GPU, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 483--489, Hiroshima, Japan, November 2016. (DOI)
  50. Naoaki Harada, Naoyuki Matsumoto, Koji Nakano and Yasuaki Ito, A hardware sorter for almost sorted sequences, with FPGA implementations, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 565--571, Hiroshima, Japan, November 2016. (DOI, Best paper award)
  51. Keisuke Nakata and Yasuaki Ito, An Evaluation of the Parallella Architecture for the Convex Hull Computation, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 704--706, Hiroshima, Japan, November 2016. (DOI)
  52. Hiroki Tokura, Takumi Honda, Yasuaki Ito, Koji Nakano, Mitsuya Nishino, Yushiro Hirota and Masami Saeki, GPU-Accelerated Bulk Computation of the Eigenvalue Problem for Many Small Real Non-symmetric Matrices, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 490--496, Hiroshima, Japan, November 2016. (DOI)
  53. Toru Fujita, Koji Nakano, Yasuaki Ito, Bitwise Parallel Bulk Computation on the GPU, with Application to the CKY Parsing for Context-Free Grammars, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 589-598, Chicago, USA, May 2016.(DOI)
  54. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of LZW Decompression in the FPGA, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 599--607, Chicago, USA, May 2016. (DOI)
  55. Koji Nakano, Shunji Funasaka, Yasuaki Ito, Fully Parallelized Lossless LZW decompression for CUDA-enabled GPUs, in Poster in the GPU Technology Conference (GTC 2016), San Jose, USA, May 2016.
  56. Toru Fujita, Daigo Nishikori, Koji Nakano, Yasuaki Ito, Efficient GPU implementations for the Conway's Game of Life, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 11--20, Sapporo, Japan, December 2015. (DOI)
  57. Tatsuya Kawamoto, Yasuaki Ito, Koji Nakano, A flexible-length-arithmetic processor based on FDFM approach in FPGAs, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 364--370, Sapporo, Japan, December 2015. (DOI)
  58. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, Parallelization Techniques for Error Diffusion with GPU Implementations, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 30--39, Sapporo, Japan, December 2015. (DOI, Best paper award)
  59. Lucas Saad, Jacir Bordim, Koji Nakano, Yasuaki Ito, A Fast Approximate String Matching Algorithm on GPU, Proc. International Symposium on Computing and Networking (CANDAR), pp. 188--192, Sapporo, Japan, December 2015. (DOI, Outstanding paper award)
  60. Takumi Honda, Yasuaki Ito, Koji Nakano, A Warp-synchronous Implementation for Multiple-length Multiplication on the GPU, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 96--102, Sapporo, Japan, December 2015. (DOI)
  61. Shunji Funasaka, Koji Nakano, Yasuaki Ito, Fast LZW compression using a GPU, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 303--308, Sapporo, Japan, December 2015. (DOI)
  62. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, A Parallel Algorithm for LZW decompression, with GPU implementation, Proc. of 11th International Conference of Parallel Processing and Applied Mathematics (PPAM 2015, LNCS 9573), pp. 228--237, Krakow, Poland, September 2015. (DOI)
  63. Xin Zhou, Koji Nakano, and Yasuaki Ito, Parallel FDFM Approach for Computing GCDs Using the FPGA, Proc. of 11th International Conference of Parallel Processing and Applied Mathematics (PPAM 2015, LNCS 9573), pp. 238--247, Krakow, Poland, September 2015. (DOI)
  64. Naoyuki Matsumoto, Koji Nakano and Yasuaki Ito, Optimal Parallel Hardware K-Sorter and TopK-Sorter, with FPGA implementations, Proc. of the 14th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 138--147, Limassol, Cyprus, June 2015. (DOI)
  65. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, GPU-accelerated Digital Halftoning by the Local Exhaustive Search, Proc. of the 14th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 82--87, Limassol, Cyprus, June 2015. (DOI)
  66. Toru Fujita, Koji Nakano and Yasuaki Ito, Bulk GCD Computation Using a GPU to Break Weak RSA Keys, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 385--394, Hyderabad, India, May 2015. (DOI)
  67. Koji Nakano and Yasuaki Ito, Optimality of Fundamental Parallel Algorithms on the Hierarchical Memory Machine, with GPU implementation, Proc. of International Conference on Parallel, Distributed and Network-Based Processing, pp.626--634, Turku, Finland, March 2015. (DOI)
  68. Xin Zhou, Yasuaki Ito, and Koji Nakano, An Efficient Implementation of the One-Dimensional Hough Transform Algorithm for Circle Detection on the FPGA, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 447--452, Shizuoka, Japan, December 2014. (DOI)
  69. Satoshi Okamoto, Yasuaki Ito, Koji Nakano, and Jacir L. Bordim, Thorough Evaluation of GPU Shared Memory Load and Store Instructions, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 614--616, Shizuoka, Japan, December 2014. (DOI)
  70. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, Proc. of International Conference on Parallel Processing, pp.251--260, Minneapolis, USA, September 2014. (DOI)
  71. Koji Nakano, Susumu Matsumae, Yasuaki Ito, Random Address Permute Shift Technique for the Shared Memory on GPUs, Proc. of International Conference on Parallel Processing Workshops, pp. 429--438, Minneapolis, USA, September 2014. (DOI)
  72. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, A GPU Implementation of Clipping-Free Halftoning using the Direct Binary Search, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 8630), pp. 57--70, Dalian, China, August 2014. (DOI)
  73. Takumi Honda, Yasuaki Ito and Koji Nakano, GPU-accelerated Verification of the Collatz Conjecture, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP, LNCS 8630), pp. 483--496, Dalian, China, August 2014. (DOI)
  74. Daisuke Takafuji, Koji Nakano and Yasuaki Ito, C2CU : A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 8631), pp. 178--191, Dalian, China, August 2014. (DOI)
  75. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 762--770, Phoenix, USA, May 2014. (DOI)
  76. Kazuya Tani, Daisuke Takafuji, Koji Nakano, Yasuaki Ito, Bulk Execution of Oblivious Algorithms on the Unified Memory Machine, with GPU Implementation, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 586--595, Phoenix, USA, May 2014. (DOI)
  77. Koji Nakano, Susumu Matsumae and Yasuaki Ito, The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 95--103, Matsuyama, Japan, December 2013. (DOI)
  78. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 75--84, Matsuyama, Japan, December 2013. (DOI)
  79. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito and Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 194--200, Matsuyama, Japan, December 2013. (DOI)
  80. Kaoru Hashimoto, Yasuaki Ito and Koji Nakano, Template Matching using DSP slices on the FPGA, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 338--344, Matsuyama, Japan, December 2013. (DOI)
  81. Ryosuke Nakamura, Yasuaki Ito and Koji Nakano, TinyCSE: Tiny Computer System for Education, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 639--641, Matsuyama, Japan, December 2013. (DOI)
  82. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, in Proc. of 2013 International Conference on Parallel Processing (ICPP), pp. 1--10, Lyon, France, October 2013. (DOI)
  83. Duhu Man, Koji Nakano and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 79--84, Tokyo, Japan, September 2013. (DOI)
  84. Xin Zhou, Yasuaki Ito and Koji Nakano, An Efficient Implementation of the Hough Transform using DSP slices and block RAMs on the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 85--90, Tokyo, Japan, September 2013. (DOI)
  85. Yuki Ago, Koji Nakano and Yasuaki Ito, A Classification Processor for a Support Vector Machine with embedded DSP slices and block RAMs in the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), Tokyo, Japan, pp. 91--96, September 2013. (DOI)
  86. Xin Zhou, Norihiro Tomagou, Yasuaki Ito and Koji Nakano, Efficient Hough Transform on the FPGA using DSP slices and Block RAMs, in Proc. of Workshop on Advances in Parallel and Distributed Computational Models (APDCM), pp. 771--778, Boston, USA, May 2013. (DOI)
  87. Akihiro Uchida, Yasuaki Ito and Koji Nakano, An Efficient GPU Implementation of Ant Colony Optimization for the Traveling Salesman Problem, Proc. of International Conference on Networking and Computing (ICNC), pp. 94--102, Okinawa, Japan, December 2012. (DOI)
  88. Akihiko Kasagi, Koji Nakano and Yasuaki Ito, An Implementation of Conflict-Free Offline Permutation on the GPU, Proc. of International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 226--232, Okinawa, Japan, December 2012. (DOI)
  89. Edans Sandes, Jacir L. Bordim, Alba C. M. A. Melo and Yasuaki Ito, Record Route Elimination (RRE): An Energy-Efficient Broadcast Algorithm, Proc. of International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 247--253, Okinawa, Japan, December 2012. (DOI)
  90. Kazufumi Nishida, Koji Nakano, Yasuaki Ito, Accelerating Dynamic Programming for the Optimal Polygon Triangulation on the GPU, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP, LNCS 7439), pp. 1--15, Fukuoka, Japan, September 2012. (DOI)
  91. Duhu Man, Kenji Uda, Yasuaki Ito, and Koji Nakano, A GPU Implementation of Computing Euclidean Distance Map with Efficient Memory Access, Proc. of International Conference on Networking and Computing (ICNC), pp. 68--76, Osaka, Japan, December 2011. (DOI)
  92. Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito, An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles, Proc. of International Conference on Networking and Computing (ICNC), pp. 77--86, Osaka, Japan, December 2011. (DOI)
  93. Yuki Ago, Atsuo Inoue, Koji Nakano, and Yasuaki Ito, The Parallel FDFM Processor Core Approach for Neural Networks, Proc. of International Conference on Networking and Computing (ICNC), pp. 113--119, Osaka, Japan, December 2011. (DOI)
  94. Akihiro Uchida, Yasuaki Ito, and Koji Nakano, Fast and Accurate Template Matching using Pixel Rearrangement on the GPU, Proc. of International Conference on Networking and Computing (ICNC), pp. 153--159, Osaka, Japan, December 2011. (DOI)
  95. Yasuaki Ito, Kouhei Ogawa, and Koji Nakano, Fast Ellipse Detection Algorithm using Hough Transform on the GPU, Proc. of International Workshop on Challenges on Massively Parallel Processors (CMPP), pp. 313--319, Osaka, Japan, December 2011. (DOI)
  96. Kazufumi Nishida, Yasuaki Ito, and Koji Nakano, Accelerating the Dynamic Programming for the Matrix Chain Product on the GPU, Proc. of International Workshop on Challenges on Massively Parallel Processors (CMPP), pp. 320--326, Osaka, Japan, December 2011. (DOI)
  97. Bo Song, Yasuaki Ito, and Koji Nakano, CRT-based Decryption using DSP blocks on the Xilinx Virtex-6 FPGA, Proc. of Workshop on Advances in Parallel and Distributed Computational Models, pp. 527--536, Anchorage, Alaska USA, May 2011. (DOI)
  98. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito, and Koji Nakano, Implementations of Parallel Computation of Euclidean Distance Map in Multicore Processors and GPUs, Proc. of International Conference on Networking and Computing (ICNC), pp. 120--127, Hiroshima, Japan, November 2010. (DOI)
  99. Bo Song, Kensuke Kawakami, Koji Nakano, and Yasuaki Ito, An RSA Encryption Hardware Algorithm Using a Single DSP Block and a Single Block RAM on the FPGA, Proc. of International Conference on Networking and Computing (ICNC), pp. 140--147, Hiroshima, Japan, November 2010. (DOI)
  100. Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito, A Rewriting Algorithm to Generate AROM-free Fully Synchronous Circuits, Proc. of International Conference on Networking and Computing (ICNC), pp. 148--155, Hiroshima, Japan, November 2010. (DOI)
  101. Kohei Ogawa, Yasuaki Ito, and Koji Nakano, Efficient Canny Edge Detection Using a GPU, Proc. of International Workshop on Advances in Networking and Computing (WANC), pp. 279--280, Hiroshima, Japan, November 2010. (DOI)
  102. Yasuaki Ito, Koji Nakano, Efficient Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), Atlanta, USA, April 2010.(DOI)
  103. Duhu Man, Yasuaki Ito, and Koji Nakano, An Efficient Parallel Sorting Compatible with the Standard qsort, Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), pp. 506--511, Hiroshima, Japan, December 2009. (DOI)
  104. Masaya Nakagawa, Duhu Man, Yasuaki Ito, and Koji Nakano, A Simple Parallel Convex Hull Algorithm for Sorted Points and the Performance Evaluation for the Multicore Processors, Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), pp. 512--517, Hiroshima, Japan, December 2009. (DOI)
  105. Yasuaki Ito and Koji Nakano, A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Conjecture, Proc. of International Symposium on Parallel and Distributed Processing with Applications, pp. 63--70, Chengdu,China, August 2009. (DOI)
  106. Kimiharu Nishihata, Duhu Man, Yasuaki Ito, and Koji Nakano, Parallel Sampling Sorting on the Multicore Processors, Proc. of the International Conference on Applications and Principles of Information Science (APIS), pp. 233--236, Okinawa, Japan, January 2009.
  107. Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito, A Tiny Processing System for Education and Small Embedded Systems on the FPGAs, Proc. of Embedded Software Optimization (ESO), pp. 472--479, Shanghai, China, December 2008. (DOI)
  108. Koji Nakano, Yasuaki Ito, Processor, Assembler, and Compiler Design Education using an FPGA, Proc. of International Conference on Parallel and Distributed Systems (ICPADS), pp. 723--728, Melbourne, Australia, December 2008. (DOI)
  109. Yasuaki Ito, Koji Nakano, Optimized Component Labeling Algorithm for using in Medium Sized FPGAs, in Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies, pp. 171--176, Dunedin, New Zealand, December 2008. (DOI)
  110. Yasuaki Ito, Koji Nakano, Component Labeling for k-Concave Binary Images Using an FPGA, Proc. of Workshop on Advances in Parallel and Distributed Computational Models(CD-ROM of International Parallel and Distributed Processing Symposium), Miami, USA, April 2008. (DOI)
  111. Yasuaki Ito and Koji Nakano, Cluster-dot Screening by Local Exhaustive Search with Hardware Acceleration, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), Long Beach, USA, March 2007.
  112. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Randomized Leader Election Protocols in Noisy Radio Networks with a Single Transceiver, Proc. of International Symposium on Parallel and Distributed Processing and Application(LNCS 4330), pp.246--256, Sorrento, Italy, December 2006. (DOI)
  113. Yasuaki Ito and Koji Nakano and Youhei Yamagishi, Efficient Hardware Algorithm for N Choose K Counters, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), Santa Fe, USA, April 2006. (DOI)
  114. Y. Ito and K. Nakano, FM Screening by the Local Exhaustive Search with Hardware Acceleration, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), Fort Lauderdale, USA, April 2004. (DOI)
  115. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Instance-Specific Solutions to Accelerate the CKY parsing, Proc. of International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, USA, pp. 72--78, June 2003.
  116. Jacir L Bordim, Yasuaki Ito, Koji Nakano, Accelerating the CKY Parsing using FPGAs, Proc. of High Performance Computing (LNCS 2552), pp.41--51, Bangalore, India, December 2002. (DOI)

国際会議(査読なし) (International Conferences (Non-refereed))

  1. Daisuke Takafuji, Koji Nakano, Yasuaki Ito, Takashi Yazane, Junko Yano, Takumi Kato, Shiro Ozaki, Rie Mori and Ryota Katsuki, Various QUBO Formulations of the Graph Isomorphism Problem and Related Problems, 14th International Workshop on Networking, Computing, Systems, and Software, Matsue, Shimane, November 2023.
  2. Haruto Fujii, Satoki Tsuji, Yasuaki Ito and Koji Nakano, A GPU Implementation of the Two-Electron Repulsion Integral Evaluation, 14th International Workshop on Networking, Computing, Systems, and Software, Matsue, Shimane, November 2023.
  3. Ryoma Okuno, Yasuaki Ito and Koji Nakano, Photograph Quality Prediction using Convolutional Neural Networks, 13th International Workshop on Networking, Computing, Systems, and Software, Himeji, Hyogo, November 2022.
  4. Minghao Xue, Yasuaki Ito and Koji Nakano, An Art Font Generation Technique using Pix2Pix-based Networks, 13th International Workshop on Networking, Computing, Systems, and Software, Himeji, Hyogo, November 2022.
  5. Zhen Cui, Yasuaki Ito, Koji Nakano and Akihiko Kasagi, Anime-style Image Generation using GAN, The 12th International Workshop on Networking, Computing, Systems, and Software, Matsue, Shimane (Online), November 2021.
  6. Naoya Yamamoto, Koji Nakano, Yasuaki Ito, Daisuke Takafuji, A New Huffman Code for Accelerating GPU Decompression (preliminary version), The Tenth International Workshop on Networking, Computing, Systems, and Software, Nagasaki, November 2019.
  7. Naoki Matsumura, Yasuaki Ito and Koji Nakano, Iterative Inference Technique for Image-to-image Translation of Tile Art Image Generation, The Ninth International Workshop on Networking, Computing, Systems, and Software, Tokyo, June 2019.
  8. Hiroki Kataoka, Kohei Yamashita, Koji Nakano, Yasuaki Ito, Akihiko Kasagi, Tsuguchika Tabaru, An Efficient Convolutional Neural Network Computation using AVX-512 Instructions, The Ninth International Workshop on Networking, Computing, Systems, and Software, Tokyo, June 2019.
  9. Hironobu Kobayashi, Yasuaki Ito, Koji Nakano, A GPU Implementation of Non-photorealistic Stained Glass Image Generation using Voronoi Diagrams, The Ninth International Workshop on Networking, Computing, Systems, and Software, Tokyo, June 2019.
  10. Daisuke Takafuji, Koji Nakano, Yasuaki Ito, Accelerating GPU implementation of All Pairs Shortest Path Algorithm, The Ninth International Workshop on Networking, Computing, Systems, and Software, Tokyo, June 2019.
  11. Hiroki Tokura, Takahiro Nishimura, Yasuaki Ito and Koji Nakano, Fast Algorithm of Unified Layer Performing Convolution and Average Pooling on GPU, The Eighth International Workshop on Networking, Computing, Systems, and Software, Takayama, Gifu, November 2018.
  12. Takahiro Nishimura, Jacir Bordim, Yasuaki Ito and Koji Nakano, GPU implementation of the fast Smith-Waterman algorithm using BPBC technique, The Eighth International Workshop on Networking, Computing, Systems, and Software, Takayama, Gifu, November 2018.
  13. Ryota Komori, Yasuaki Ito and Koji Nakano, Acquisition of Best Bet for 10,000 Yen Game Using Machine Learning, The Eighth International Workshop on Networking, Computing, Systems, and Software, Takayama, Gifu, November 2018.
  14. Makoto Motoka, Hiroki Tokura, Koji Nakano and Yasuaki Ito, Fast Algorithm of Inventory Management using Dynamic Programming on GPU, The Eighth International Workshop on Networking, Computing, Systems, and Software, Takayama, Gifu, November 2018.
  15. Lucas Saad, Jacir Bordim, Yasuaki Ito and Koji NakanoParallel Rabin-Karp Algorithm Implementation on GPU (Preliminary Version), The Seventh International Workshop on Networking, Computing, Systems, and Software, Aomori, Aomori, November 2017.
  16. Naoaki Harada, Koji Nakano and Yasuaki ItoAn FPGA Implementation of a Parallel Column Sort Algorithm with Off-chip DRAMs, The Seventh International Workshop on Networking, Computing, Systems, and Software, Aomori, Aomori, November 2017.
  17. Ryouhei Murooka, Yasuaki Ito and Koji Nakano, GPU-accelerated Ant Colony Optimization for the Traveling Salesman Problem, The Seventh International Workshop on Networking, Computing, Systems, and Software, Aomori, Aomori, November 2017.
  18. Tomoya Baba, Yasuaki Ito and Koji Nakano, A Web-based Management System for International Academic Symposiums, The Seventh International Workshop on Networking, Computing, Systems, and Software, Aomori, Aomori, November 2017.
  19. Daisuke Takafuji, Koji Nakano and Yasuaki Ito, A CUDA C Program Generator for Verifying Logical Operators, The Seventh International Workshop on Networking, Computing, Systems, and Software, Aomori, Aomori, November 2017.
  20. Yi Yang, Yasuaki Ito and Koji Nakano, Photomosaic Generation by Rearranging Divided Images, The Sixth International Workshop on Networking, Computing, Systems, and Software, Higashi-Hiroshima, Hiroshima, November 2016.
  21. Xin Zhou, Yasuaki Ito, and Koji Nakano, An Efficient Implementation of LZW Decompression Using Block RAMs in the FPGA (Preliminary Version), The Fifth International Workshop on Networking, Computing, Systems, and Software, Sapporo, Hokkaido, December 2015.
  22. Toru Fujita, Koji Nakano and Yasuaki Ito. Bulk GCD Computation for Breaking Weak RSA Keys using a GPU, the 8th Annual Meeting of Asian Association for Algorithms and Computation (AAAC 2015), Miyajima, Hiroshima, May 2015.
  23. Naoyuki Matsumoto, Koji Nakano and Yasuaki Ito. Optimal K-Sorter and TopK-Sorter using FPGAs, the 8th Annual Meeting of Asian Association for Algorithms and Computation (AAAC 2015), Miyajima, Hiroshima, May 2015.
  24. Akihiko Kasagi, Koji Nakano and Yasuaki Ito, Implementations of Parallel Error Diffusion Optimized for GPU (Preliminary version), The Fourth International Workshop on Networking, Computing, Systems, and Software, Shizuoka, Shizuoka, December 2014.
  25. Kaoru Hashimoto, Koji Nakano and Yasuaki Ito, Accelaration of the Smith-Waterman Algorithm with traceback on the FPGA, The Fourth International Workshop on Networking, Computing, Systems, and Software, Shizuoka, Shizuoka, December 2014.
  26. Masaaki Kuwada, Koji Nakano, Yasuaki Ito and Youhei Ishihara, Defect Inspection of an Arc Welded Bead Using a Support Vector Machine and a Neural Network, The Fourth International Workshop on Networking, Computing, Systems, and Software, Shizuoka, Shizuoka, December 2014.
  27. Ryosuke Sakai, Koji Nakano and Yasuaki Ito, Accelerating RSA encryption using GPUs, The Fourth International Workshop on Networking, Computing, Systems, and Software, Shizuoka, Shizuoka, December 2014.
  28. Yuki Yamamoto, Daisuke Takafuji, Yasuaki Ito, Koji Nakano and Tomoko Kashima, Sport support system using realtime audio feedback, The Third International Workshop on Networking, Computing, Systems, and Software, Matsuyama, Ehime, December 2013.
  29. Akihiko Kasagi, Koji Nakano and Yasuaki Ito, Fast image component labeling on the GPU (Preliminary version), The Third International Workshop on Networking, Computing, Systems, and Software, Matsuyama, Ehime, December 2013.
  30. Daisuke Takafuji, Yasuaki Ito and Koji Nakano, Comparison of GPU Implementations of Row-wise and Column-wise Fundamental Algorithms, The Third International Workshop on Networking, Computing, Systems, and Software, Matsuyama, Ehime, December 2013.
  31. Xin Zhou, Yasuaki Ito and Koji Nakano, An FPGA Implementation of Hough Transform using DSP blocks and block RAMs, The Second International Workshop on Networking, Computing, Systems, and Software, Naha, Okinawa, December 2012.
  32. Yuki Ago, Yasuaki Ito and Koji Nakano, An Efficient Implementation of a Support Vector Machine in the FPGA, The Second International Workshop on Networking, Computing, Systems, and Software, Naha, Okinawa, December 2012.
  33. Norihiro Tomagou, Koji Nakano and Yasuaki Ito, An Implementation of Hough Transform on the GPU, The Second International Workshop on Networking, Computing, Systems, and Software, Naha, Okinawa, December 2012.

国内学会(査読あり) (Domestic Conferences (Refereed))

  1. Shunji Funasaka, Koji Nakano and Yasuaki Ito, GPU Applications with Single Kernel Synchronization Technique, in Poster in GPU Technology Conference (GTC Japan 2017), Tokyo, December 2017.
  2. Hiroki Tokura, Yasuaki Ito, and Koji Nakano, GPU Implementation of Image Generation for Square Pointillism, in Poster in GPU Technology Conference (GTC Japan 2017), Tokyo, December 2017.
  3. Toru Fujita, Koji Nakano, Yasuaki Ito, Bitwise Parallel Bulk Computation for CKY Parsing, with the GPU implementation, in Poster in GPU Technology Conference (GTC Japan 2016), Tokyo, October 2016.
  4. Shunji Funasaka, Koji Nakano and Yasuaki Ito, Efficient Loss-Less Data Compression, with GPU implementation, in Poster in GPU Technology Conference (GTC Japan 2016), Tokyo, October 2016.
  5. Hiroki Tokura, Takumi Honda, Yasuaki Ito, Koji Nakano, Mitsuya Nishino, Yushiro Hirota and Masami Saeki, Bulk Computation of Eigenvalues of Many Small Real Non-symmetric Matrices on the GPU, in Poster in GPU Technology Conference (GTC Japan 2016), Tokyo, October 2016.

国内学会(査読なし) (Domestic Conferences (Non-refereed))

  1. 林川雅俊, 中野浩嗣, 伊藤靖朗, 安戸僚汰, ブルームフィルタを用いたGPU上の高速パターンテスト, Proc. of the 15th Workshop on Theoretical Computer Science, pp. 1-12, Takehara, Hiroshima, September 2019.
  2. 吹田駿介, 西村崇宏, 戸倉宏樹, 中野浩嗣, 伊藤靖朗, 笠置明彦, 田原司睦, Convolution-PoolingのGPUへの効率良い実装方法, Proc. of the 15th Workshop on Theoretical Computer Science, pp. 13-21, Takehara, Hiroshima, September 2019.
  3. Shunji Funasaka, Koji Nakano, Yasuaki Ito, Single Kernel Soft Synchronization Technique for Task Arrays on CUDA-enabled GPUs, with Applications, Proc. of the 14th Workshop on Theoretical Computer Science, pp. 109--131, Iizuka, Fukuoka, September 2018.
  4. 松村 直樹，戸倉 宏樹，黒田 悠希，伊藤 靖朗，中野 浩嗣, GPU を⽤いたタイルアート⽣成の２つの⽅法, Proc. of the 14th Workshop on Theoretical Computer Science, pp. 132--150, Iizuka, Fukuoka, September 2018.
  5. 和田 啄茉, 松村 直樹, 中野 浩嗣, 伊藤 靖朗, FPGA へのブルームフィルタの効率よい実装法, Proc. of the 14th Workshop on Theoretical Computer Science, pp. 158--174, Iizuka, Fukuoka, September 2018.
  6. 小森 亮太, 伊藤 靖朗, 中野 浩嗣, １万円ゲームの最強戦略, Proc. of the 14th Workshop on Theoretical Computer Science, pp. 181--194, Iizuka, Fukuoka, September 2018. (優秀研究賞)
  7. 松村 直樹，戸倉 宏樹，黒田 悠希，伊藤 靖朗，中野 浩嗣, 局所探索と機械学習を用いたタイルアート画像生成手法, Technical Report of IPSJ, Vol. 2018-AL-169, No. 4, Otaru, Hokkaido, September 2018.
  8. 佐伯 和人，伊藤 靖朗，中野 浩嗣, FPGAを用いたコラッツ予想の網羅的検証の高速化, Technical Report of IPSJ, Vol. 2018-AL-169, No. 5, Otaru, Hokkaido, September 2018.
  9. 船坂峻慈, 中野浩嗣, 伊藤靖朗, 単一カーネル同期テクニックを用いたGPUアプリケーション, IEICE Technical Report, Vol. 117, No. 314, IEICE-CPSY2017-56, pp. 33--38, Aomori, Aomori, November 2017.
  10. 戸倉宏樹, 黒田悠希, 伊藤靖朗, 中野浩嗣, 正方形点描画像生成のGPU実装, IEICE Technical Report, Vol. 117, No. 314, IEICE-CPSY2017-57, pp. 39--44, Aomori, Aomori, November 2017.
  11. 和田啄茉, 船坂峻慈, 中野浩嗣, 伊藤靖朗, 近似文字列マッチングのハイブリッドアーキテクチャとそのFPGA実装, IEICE Technical Report, Vol. 117, No. 314, IEICE-CPSY2017-57, pp. 45--58, Aomori, Aomori, November 2017.
  12. 本田啓朗, 本田巧, 山元晨之介, 中野浩嗣, 伊藤靖朗, ボロノイ図とユークリッド距離マップ計算のGPU実装, IEICE Technical Report, Vol. 117, No. 153, IEICE-CPSY2017-18, pp. 13--18, Akita, Akita, July 2017.
  13. 柄本悠太郎, 本田巧, 中野浩嗣, 伊藤靖朗, Summed Area Table計算の効率的なGPU実装, IEICE Technical Report, Vol. 117, No. 153, IEICE-CPSY2017-19, pp. 19--24, Akita, Akita, July 2017.
  14. Kohei Yamashita, Yasuaki Ito, Koji Nakano, Bulk Execution of the Dynamic Programming for the Optimal Polygon Triangulation on the GPU, IEICE Technical Report, Vol. 117, No. 28, IEICE-COMP2017-3, pp. 17--22, Nagasaki, Nagasaki, May 2017.
  15. Takahiro Nishimura, Jacir L. Bordim, Yasuaki Ito, Koji Nakano, A GPU Implementation of the Smith-Waterman Algorithm using Bitwise Parallel Bulk Computation Technique, IEICE Technical Report, Vol. 117, No. 28, IEICE-COMP2017-4, pp. 23--30, Nagasaki, Nagasaki, May 2017.
  16. Hiroki Tokura, Takumi Honda, Yasuaki Ito, Koji Nakano, Mitsuya Nishino, Yushiro Hirota, Masami Saeki, A GPU Implementation of Eigenvalue Computation for a Large Number of Matrices, IEICE Technical Report, Vol. 116, No. 240, IEICE-CPSY2016-45, pp. 13--18, Chiba, Chiba, October 2016.
  17. Shunji Funasaka, Koji Nakano, Yasuaki Ito, A Loss-Less Data Compression Algorithm for GPUs, IEICE Technical Report, Vol. 116, No. 240, IEICE-CPSY2016-46, pp. 19--24, Chiba, Chiba, October 2016.
  18. Xin Zhou, Yasuaki Ito, Koji Nakano, An FPGA Implementation of LZW Compression, IEICE Technical Report, Vol. 116, No. 177, IEICE-CPSY2016-11, pp. 7--12, Matsumoto, Nagano, August 2016.
  19. Toru Fujita, Koji Nakano and Yasuaki Ito, A GPU Implementation of the CKY Parsing using Bitwise Parallel Bulk Computation , IEICE Technical Report, Vol. 116, No. 177, IEICE-CPSY2016-12, pp. 13--18, Matsumoto, Nagano, August 2016.
  20. 松本 直之, 周 昕, 中野 浩嗣, 伊藤 靖朗, FPGAを用いたハードウェアソーティングアルゴリズムの実装, IEICE Technical Report, Vol. 115, No. 447, IEICE-ICD2015-103, pp. 37--42, Higashi-Hiroshima, Hiroshima, March 2016.
  21. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of LZW Decompression on the FPGA, IEICE Technical Report, Vol. 115, No. 447, IEICE-ICD2015-104, pp. 43--48, Higashi-Hiroshima, Hiroshima, March 2016.
  22. Takumi Honda, Yasuaki Ito, Koji Nakano, A Warp-synchronous Implementation for Multiple-length Multiplication on the GPU, Proc. of The 11th Workshop on Theoretical Computer Science, pp. 100--106, Kita-Nagoya, Aichi, September 2015.
  23. Toru Fujita, Daigo Nishikori, Koji Nakano and Yasuaki Ito, Efficient GPU implementations for the Conway’s Game of Life, Proc. of The 11th Workshop on Theoretical Computer Science, pp. 169--178, Kita-Nagoya, Aichi, September 2015.
  24. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, A Parallel Algorithm for LZW decompression, with GPU implementation, Proc. of The 11th Workshop on Theoretical Computer Science, pp. 179--188, Kita-Nagoya, Aichi, September 2015.
  25. 本田 巧, 伊藤 靖朗, 中野 浩嗣, GPU向け多倍長整数乗算, IEICE Technical Report, Vol. 115, No. 174, CPSY2015-22, pp. 79--84, Beppu, Oita, August 2015.
  26. Shunji Funasaka, Yasuaki Ito, Koji Nakano, A Parallel Algorithm for LZW decompression, with GPU implementation, IEICE Technical Report, Vol. 115, No. 174, CPSY2015-24, pp. 91--96, Beppu, Oita, August 2015.
  27. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Implementations of Parallel Error Diffusion Optimized for GPU, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-57, pp. 19--24, Higashihiroshima, Hiroshima, November 2014.
  28. Daisuke Takafuji, Yasuaki Ito, and Koji Nakano, C2CU: A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-67, pp. 75--80, Higashihiroshima, Hiroshima, November 2014.
  29. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Verification of the Collatz Conjecture, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-68, pp. 81--86, Higashihiroshima, Hiroshima, November 2014.
  30. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, A GPU Implementation of Clipping-Free Halftoning using the Direct Binary Search, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-69, pp. 87--92, Higashihiroshima, Hiroshima, November 2014.
  31. 谷 和也, 中野 浩嗣, 伊藤 靖朗, GPUを用いた高スループット計算システムの実装, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-70, pp. 93--98, Higashihiroshima, Hiroshima, November 2014.
  32. 酒井 亮輔, 中野 浩嗣, 伊藤 靖朗, GPUを用いたRSA暗号の高速化, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-71, pp. 99--104, Higashihiroshima, Hiroshima, November 2014.
  33. Xin Zhou, Yasuaki Ito, and Koji Nakano,　An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA, IEICE Technical Report, Vol. 114, No. 155, CPSY2014-12, pp. 13--18, Niigata, Niigata, July 2014.
  34. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, IEICE Technical Report, Vol. 114, No. 155, CPSY2014-23, pp. 79--84, Niigata, Niigata, July 2014.
  35. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  36. Xin Zhou, Yasuaki Ito, and Koji Nakano, An Efficient Implementation of the Gradient-Based Hough Transform Using DSP Blocks and Block RAMs on the FPGA, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  37. Daisuke Takafuji, Yasuaki Ito, and Koji Nakano, C2CU: A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  38. Koji Nakano, Susumu Matsumae, and Yasuaki Ito, Random Address Permute-Shift Technique for the Shared Memory on GPUs, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  39. 高下 孔明, 伊藤 靖朗, 中野 浩嗣, GPUを用いたClipping-free Direct Binary Searchの高速化, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  40. 本田 巧, 伊藤 靖朗, 中野 浩嗣, GPUを用いたコラッツ予想検証の高速化, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  41. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano, and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, IEICE Technical Report, Vol. 113, No. 324, CPSY2013-69, pp. 59--64, Kagoshima, Kagoshima, November 2013.
  42. Ryoshuke Nakamura and Yasuaki Ito and Koji Nakano, TinyCSE: Tiny Computer System for Education, IEICE Technical Report, Vol. 113, No. 324, CPSY2013-66, pp. 41--45, Kagoshima, Kagoshima, November 2013.
  43. Manduhu, Koji Nakano, and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, IEICE Technical Report, Vol. 113, No. 282, CPSY2013-41, pp. 13--18, Higashihiroshima, Hiroshima, November 2013.
  44. 蓬郷 典大, 中野 浩嗣, 伊藤 靖朗, GPUを用いたハフ変換の実装, IEICE Technical Report, Vol. 113, No. 282, CPSY2013-42, pp. 19--24, Higashihiroshima, Hiroshima, November 2013.
  45. Duhu Man, Koji Nakano, and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 15--20, Karatsu, Saga, September 2013.
  46. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano, and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, with Performance Evaluation, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 21--30, Karatsu, Saga, September 2013.
  47. Koji Nakano, Susumu Matsumae, and Yasuaki Ito, The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 83--91, Karatsu, Saga, September 2013.
  48. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 92--101, Karatsu, Saga, September 2013.
  49. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito, Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 102--108, Karatsu, Saga, September 2013.
  50. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito, and Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, IEICE Technical Report, Vol. 113, No. 169, CPSY2013-15, pp. 31--35, Kitakyushu, Fukuoka, August 2013.
  51. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, Vol. 113, No. 169, CPSY2013-16, pp. 37--42, Kitakyushu, Fukuoka, August 2013.
  52. Kaoru Hashimoto, Yasuaki Ito, Koji Nakano, Template Matching using DSP slices on the FPGA, Vol. 113, No. 169, CPSY2013-17, pp. 43--48, Kitakyushu, Fukuoka, August 2013.
  53. Xin Zhou, Yasuaki Ito, and Koji Nakano, An implementation of Hough Transform Using DSP blocks and block RAMs on the FPGA, IEICE Technical Report, Vol. 112, No. 237, CPSY2012-31, pp. 1--6, Higashihiroshima, Hiroshima, October 2012.
  54. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, A GPU Implementation of Conflict-Free Offline Permutation, IEICE Technical Report, Vol. 112, No. 237, CPSY2012-35, pp. 25--30, Higashihiroshima, Hiroshima, October 2012.
  55. Akihiro Uchida, Yasuaki Ito, Koji Nakano, An Efficient Implementation of Ant Colony Optimization for the Traveling Salesman Problem on the GPU, IEICE Technical Report, Vol. 112, No. 237, CPSY2012-36, pp. 31--36, Higashihiroshima, Hiroshima, October 2012.
  56. Xin Zhou, Yasuaki Ito, and Koji Nakano, Fast Hough Transform Using DSP blocks and block RAMs on the FPGA, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 27--33, Kobe, Hyogo, September 2012.
  57. Kazufumi Nishida, Koji Nakano, and Yasuaki Ito, Accelerating Dynamic Programming for the Optimal Polygon Triangulation on the GPU, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 34--41, Kobe, Hyogo, September 2012.
  58. Akihiro Uchida, Yasuaki Ito, Koji Nakano, An Efficient GPU Implementation of Ant Colony Optimization for the Traveling Salesman Problem, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 42--50, Kobe, Hyogo, September 2012.
  59. Duhu Man, Kenji Uda, Yasuaki Ito and Koji Nakano, Accelerating Computation of Euclidean Distance Map using the GPU with Efficient Memory Access, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 51--63, Kobe, Hyogo, September 2012.
  60. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Implementation of Data Permutation on the GPU, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 113--119, Kobe, Hyogo, September 2012.
  61. Yuki Agou, Yasuaki Ito, Koji Nakano, An FPGA Implementation for a 3-layer Perceptron with the FDFM Processor Core Approach, IEICE Technical Report, Vol. 112, No. 70, RECONF2012-8, pp. 43--48, Naha, Okinawa, May 2012.
  62. Yasuaki Ito, Koji Nakano, and Bo Song, The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption, Proc. of The 7th Workshop on Theoretical Computer Science, pp. 103--113, Fukuma, Fukuoka, September 2011.
  63. Yuki Ago, Atsuo Inoue, Koji Nakano, Yasuaki Ito, The Parallel FDFM Processor Core Approach for Neural Networks, Proc. of The 7th Workshop on Theoretical Computer Science, pp. 114--120, Fukuma, Fukuoka, September 2011.
  64. Akihiro Uchida, Yasuaki Ito, and Koji Nakano, Fast and Accurate Template Matching using Pixel Rearrangement on the GPU, Proc. of The 7th Workshop on Theoretical Computer Science, pp. 167--172, Fukuma, Fukuoka, September 2011.
  65. 伊藤靖朗, 中野浩嗣, FPGA のDSP ブロックを用いた高速計算, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 70--75, Nagashima, Mie, September 2010.
  66. Bo Song, Kensuke Kawakami, Koji Nakano and Yasuaki Ito, An RSA Encryption using DSP slices and Block RAMs on the FPGA, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 76--84, Nagashima, Mie, September 2010.
  67. Md. Nazrul Islam Mondal, Koji Nakano and Yasuaki Ito, An Algorithm to Remove Asynchronous ROMs, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 85--92, Nagashima, Mie, September 2010.
  68. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito and Koji Nakano, Implementations of Parallel Euclidean Distance Map Computation in Multicore Processors and GPUs, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 93--100, Nagashima, Mie, September 2010.
  69. Yasuaki Ito and Koji Nakano, An Effcient Implementation of Exaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs, IEICE Technical Report, Vol. 110, No. 32, RECONF2010-15, pp. 69--74, Nagasaki, May 2010.
  70. Yasuaki Ito and Koji Nakano, Component Labeling on the FPGA using Few Logic Elements, IEICE Technical Report, Vol. 109, No. 198, RECONF2009-20, pp. 7--12, Utsunomiya, September 2009.
  71. Koji Nakano, Yasuaki Ito, Kensuke Kawakami, Koji Shigemoto, An FPGA-based Tiny Processing System for Small Embedded System and Education, IEICE Technical Report, Vol. 109, No. 198, RECONF2009-32, pp. 79--84, Utsunomiya, September 2009.
  72. Yasuaki Ito and Koji Nakano, An FPGA-based Architecture for Verifying Collatz Conjecture, IEICE Technical Report, Vol. 109, No. 198, RECONF2009-40, pp. 125--130, Utsunomiya, September 2009.
  73. Yasuaki Ito and Koji Nakano, A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Conjecture, Proc. of The 5th Workshop on Theoretical Computer Sciences, pp.7--14, Hiroshima, September 2009.
  74. 中河雅弥，伊藤靖朗，中野浩嗣, 並列凸包計算アルゴリズムのマルチコアプロセッサ上での評価, Proc. of The 5th Workshop on Theoretical Computer Science, pp. 67--68, Hiroshima, September 2009.
  75. Duhu Man , Yasuaki Ito and Koji Nakano, Parallel Sampling Sorting on the Multicore Processors, Proc. of The 5th Workshop on Theoretical Computer Science, pp. 69--70, Hiroshima, September 2009.
  76. 伊藤靖朗, 同期ブロックRAMの非同期ブロックRAMへの変換について, Proc. of The 4th Workshop on Theoretical Computer Sciences, pp.151--157, Nagahama, Shiga, September 2008.
  77. Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, and Yasuaki Ito, A Tiny Processing System for Education and Small Embedded System on the FPGA, Proc. of The 4th Workshop on Theoretical Computer Sciences, pp.135--142, Nagahama, Shiga, September 2008.
  78. Yasuaki Ito and Koji Nakano, Component Labeling for k-Concave Binary Images Using an FPGA, IEICE Technical Report, Vol. 107, No. 390, COMP2007-48, pp. 1--8, Hiroshima, December 2007.
  79. 伊藤靖朗, 中野浩嗣, FPGAを用いた二値画像のラベリング, Proc. of The 3rd Workshop on Theoretical Computer Sciences, pp.6--12, Mojiko, Fukuoka, September 2007.
  80. 伊藤 靖朗, 中野 浩嗣，山岸 洋平, n Choose k カウンタのハードウェア実装とその応用, Proc. of The 2nd Workshop on Theoretical Computer Sciences, pp.68--69, Seto, Aichi,September 2006.
  81. 伊藤 靖朗, 中野 浩嗣, FPGAを用いた相関係数による画像のパターンマッチング,　2006年度 夏のLAシンポジウム, Hiroshima, August 2006.
  82. 伊藤 靖朗, 中野 浩嗣, FPGAを用いた大きな文法のCKYパージング, 平成16年度電気・情報関連学会中国支部第55回連合大会講演論文集, p.308, Ube, Yamaguchi, September 2004.
  83. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Instance-Specific Solutions for the CKY Parsing, 第１回 リコンフィギャラブル研究会 論文集, pp.27-33, Kumamoto, September 2003.
  84. Y. Ito, J. L. Bordim, and K. Nakano, Accelerating the CKY Parsing using FPGAs, Technical Report of IPSJ, AL2002-85 , pp. 35-42, Tokyo, July 2002.

表彰

  1. Outstanding paper award, The Tenth International Symposium on Computing and Networking (Haiya Huang, Yasuaki Ito, Koji Nakano, A Bokeh Image Generation Technique Using Machine Learning), November 2022.
  2. Best paper award, The 6th International Workshop on GPU Computing and AI (Jiamian Huang, Yasuaki Ito and Koji Nakano, A GPU Implementation of Watercolor Painting Image Generation), November 2021.
  3. Best paper award, The Eighth International Symposium on Computing and Networking (Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano, Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA), November 2020.
  4. Best paper award, The 5th International Workshop on GPU Computing and AI (Ye Yuan, Yasuaki Ito, and Koji Nakano, Art Font Image Generation with Conditional Generative Adversarial Networks), November 2020.
  5. Best Paper Award, 49th International Conference on Parallel Processing (Naoya Yamamoto, Koji Nakano, Yasuaki Ito, and Daisuke Takafuji, Akihiko Kasagi, Tsuguchika Tabaru, Huffman Coding with Gap Arrays for GPU Acceleration), August 2020.
  6. Best paper award, The 4th International Workshop on GPU Computing and AI (Naoki Matsumura, Yasuaki Ito, Koji Nakano, Akihiko Kasagi and Tsuguchika Tabaru, Structured Sparse Fully-Connected Layers in the CNNs and its GPU Acceleration), November 2019.
  7. Best paper award, The Sixth International Symposium on Computing and Networking (Takuma Wada, Naoki Matsumura, Koji Nakano and Yasuaki Ito, Efficient Byte Stream Pattern Test using Bloom Filter with Rolling Hash Functions on the FPGA), November 2018.
  8. 2018年 9月 優秀研究賞 (小森良太, 伊藤靖朗, 中野浩嗣, 10000円ゲームの最強戦略), 第14回情報科学ワークショップ
  9. Outstanding paper award, The Fifth International Symposium on Computing and Networking (Hiroki Tokura, Yuki Kuroda, Yasuaki Ito, and Koji Nakano, A Square Pointillism Image Generation, and its GPU Acceleration), November 2017.
  10. Best paper award, The 8th International Workshop on Parallel and Distributed Algorithms and Applications (Naoaki Harada, Naoyuki Matsumoto, Koji Nakano and Yasuaki Ito, A Hardware Sorter for Almost Sorted Sequences, with FPGA Implementations), November 2016.
  11. Best paper award, The Third International Symposium on Computing and Networking (Akihiko Kasagi, Koji Nakano and Yasuaki Ito, Parallelization Techniques for Error Diffusion with GPU Implementations), December 2015.
  12. Outstanding paper award, The Third International Symposium on Computing and Networking (Lucas Saad, Jacir Bordim, Koji Nakano and Yasuaki Ito, A Fast Approximate String Matching Algorithm on GPU), December 2015.
  13. 2009年11月 平成２１年度広島大学大学院工学研究科・工学部教育顕彰
  14. 2005年 5月 平成１６年度電子情報通信学会中国支部奨励賞
  15. 2003年 3月 北陸先端科学技術大学院大学 優秀学生賞

外部資金

  • 2021--2023年度 科学研究費助成事業（学術研究助成基金助成金（基盤研究(B)）「超並列システム向け可逆データ圧縮法の提案と実用化」(分担)
  • 令和2--4年度 科学研究費助成事業（学術研究助成基金助成金（基盤研究(C)）「回路シミュレーションによるGPU向け超並列機械学習計算環境の構築」(代表)
  • 平成31年度(令和元年度） 戦略的情報通信研究開発推進事業（SCOPE） 平成31年度電波有効利用促進型研究開発（先進的電波有効利用型）フェーズⅠ 「高スループットデータ処理機能を備えた300GHz帯無線-光通信インタフェースの研究開発」（分担）
  • 平成28--30年度 科学研究費助成事業（学術研究助成基金助成金（基盤研究(C)）「GPU向けビットレベル並列化による超ハイスループット計算」(代表)
  • 平成26--30年度 科学研究費助成事業（学術研究助成基金助成金（基盤研究(B)））「メモリマシンモデル上の並列計算理論の構築と次世代ＧＰＧＰＵアーキテクチャの提案」（分担）
  • 平成28--29年度 科学研究費助成事業（学術研究助成基金助成金（挑戦的萌芽研究））「ヘテロ並列計算システムによる低消費電力・超線形加速計算とそのための開発環境」(分担)
  • 平成25年度 電気通信普及財団「FPGA向け超高速画像処理システム開発環境の構築」(単独)
  • 平成25--27年度 科学研究費助成事業（学術研究助成基金助成金（挑戦的萌芽研究））「FPGAを用いた汎用計算技術GPFPGAを実現するための開発環境の構築」（分担）
  • 平成24--27年度 科学研究費助成事業（学術研究助成基金助成金（若手研究(B)）「ＦＰＧＡ向けメニーコアアーキテクチャによる計算高速化」(単独)
  • 平成22年度 組織的な若手研究者等海外派遣プログラム (理工農系：サステナブル社会の実現に貢献する自然科学系国際的若手研究者の育成プログラム) 「センサーネットワークにおけるリコンフィギュラブルデバイスの応用」（派遣先：ブラジル ブラジリア大学、2010/12--2011/2、単独）
  • 平成21--24年度 科学研究費補助金 基盤研究(C)「FPGAの抽象モデル化とハードウェアアルゴリズムの評価」（分担）
  • 平成20--23年度 科学研究費補助金 若手研究(B) 「部分計算によるFPGAを用いた計算高速化理論の確立」(単独)
  • 平成20年度 電気通信普及財団「並列アルゴリズムのIPコアライブラリの構築に関する研究」(単独)
  • 平成17--20年度 科学研究費補助金 基盤研究(B)「アドホックネットワークの実用化に向けた省電力通信プロトコルの研究」（分担）
  • 平成17--19年度 科学研究費補助金 萌芽研究「リコンフィギュラブルコンピューティング向け簡易開発環境の構築」（分担）

講義担当

  • 2023年度

    • ゼロからはじめるプログラミング（学部１年生）
    • プログラミングIII（学部２年生）
    • オペレーティングシステム（学部２年生）
    • Embedded System（大学院）

  • 2022年度

    • プログラミングIII（学部２年生）
    • オペレーティングシステム（学部２年生）
    • Embedded System（大学院）

  • 2021年度

    • プログラミングIII（学部２年生）
    • オペレーティングシステム（学部２年生）
    • Embedded System（大学院）

  • 2020年度

    • プログラミングIII（学部２年生）
    • オペレーティングシステム（学部２年生）
    • 教養ゼミ（学部１年生）
    • Embedded System（大学院）

  • 2019年度

    • プログラミングIII（情報科学部２年生）
    • オペレーティングシステム（情報科学部２年生、工学部３年生）
    • Embedded Software（大学院）
    • 情報工学演習III（工学部３年生）
    • 技術英語演習（研究室担当、工学部３年生）

  • 2018年度

    • オペレーティングシステム（学部３年生）
    • Embedded Software（大学院）
    • 情報工学演習III（学部３年生）
    • 技術英語演習（研究室担当、学部３年生）

  • 2017年度

    • オペレーティングシステム（学部３年生）
    • Embedded Software（大学院）(広島大学の名講義(工学研究科))
    • 教養ゼミ（学部１年生）
    • 情報工学演習III（学部３年生）
    • 技術英語演習（研究室担当、学部３年生）
    • エネルギーと情報システム応用概論（オムニバス形式、１回担当、学部１年生）

  • 2016年度

    • オペレーティングシステム（学部３年生）
    • Embedded Software（大学院）
    • 教養ゼミ（学部１年生）
    • 情報工学演習II（学部３年生）
    • 技術英語演習（研究室担当、学部３年生）
    • エネルギーと情報システム応用概論（オムニバス形式、１回担当、学部１年生）

  • 2015年度

    • オペレーティングシステム（学部３年生）
    • Embedded Software（大学院）
    • 教養ゼミ（学部１年生）
    • 情報工学演習I（学部２年生）
    • 情報工学演習II（学部３年生）
    • 技術英語演習（研究室担当、学部３年生）
    • プログラミング序説（端末室担当、学部１年生）
    • エネルギーと情報システム応用概論（オムニバス形式、１回担当、学部１年生）

  • 2014年度

    • オペレーティングシステム（学部３年生）
    • Embedded Software（大学院）
    • 教養ゼミ（学部１年生）
    • 情報工学演習I（学部２年生）
    • 情報工学演習II（学部３年生）
    • 技術英語演習（研究室担当、学部３年生）
    • プログラミング序説（端末室担当、学部１年生）
    • システム・情報工学概論（オムニバス形式、１回担当、学部１年生）

  • 2013年度

    • オペレーティングシステム（学部３年生）
    • 教養ゼミ（学部１年生）
    • 情報工学演習I（学部２年生）
    • 情報工学演習II（学部３年生）
    • 技術英語演習（講義室・研究室担当、学部３年生）
    • プログラミング序説（端末室担当、学部１年生）
    • システム・情報工学概論（オムニバス形式、１回担当、学部１年生）

  • 2012年度

    • オペレーティングシステム（学部３年生）
    • 教養ゼミ（学部１年生）
    • 情報工学演習I（学部２年生）
    • 情報工学演習II（学部３年生）
    • 技術英語演習（講義室担当、学部３年生）
    • プログラミング序説（端末室担当、学部１年生）
    • プログラミング演習I（端末室担当、学部１年生）

  • 2011年度

    • 教養ゼミ（学部１年生）
    • 情報工学演習I（学部２年生）
    • 情報工学演習II（学部３年生）

  • 2010年度

    • 教養ゼミ（学部１年生）
    • 情報工学演習I（学部２年生）
    • 情報工学演習II（学部３年生）

  • 2009年度

    • 教養ゼミ（学部１年生）
    • 情報工学演習I（学部２年生）
    • 情報工学演習II（学部３年生）

  • 2008年度

    • 教養ゼミ（学部１年生）
    • 情報工学演習I（学部２年生）
    • 情報工学実験II（学部３年生）

  • 2007年度

    • 情報工学実験I（学部２年生）
    • 情報工学実験II（学部３年生）

  • 2006年度

    • 情報工学実験I（学部２年生）
    • 情報工学実験II（学部３年生）

  • 2005年度

    • 情報工学実験I（学部２年生）
    • 情報工学実験II（学部３年生）

  • 2004年度

    • 情報工学実験I（学部２年生）

その他

  • 2023年度
    • 模擬授業(島根県立浜田高等学校)
      • AI・機械学習入門

  • 2021年度

    • 広大名講義100選「情報科学概論」第２回講義
      • AI・機械学習入門

  • 2019年度

    • 模擬授業(広島県立三原高等学校)
      • AIが人間を超える？

  • 2018年度

    • 社会人リカレント講座
      • GPUプログラミング

  • 2014年度

    • 模擬授業(広島県立広島高等学校)
      • スマートフォンを用いた組込みシステム開発

学会活動

現在の活動

  • Concurrency and Computation Practice and Experience (CCPE) special issue on CANDAR 2023, Guest Editor, 2024.
  • Workshop on Advances in Parallel and Distributed Computational Models (APDCM), Program Committee, 2008--2024.
  • International Symposium on Computing and Networking (CANDAR), Registration and Finance Chair, 2013--.
  • International Journal of Networking and Computing (IJNC), Editor, 2017--.
  • International Workshop on GPU Computing and AI (GCA), Workshop Co-chair, 2016--2023.
  • International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), Program Committee, 2012--2022.
  • 2024年電子情報通信学会総合大会 プログラム委員会 委員, 2022--2024.

以前の活動

  • Concurrency and Computation Practice and Experience (CCPE) special issue on CANDAR 2022, Guest Editor, 2023.
  • Concurrency and Computation Practice and Experience (CCPE) special issue on CANDAR 2021, Guest Editor, 2022.
  • Special Section on Special Section on Forefront Computing of IEICE Transactions on Information and Systems, Guest Associate Editor, November 2021--December 2022.
  • Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking of IEICE Transactions on Information and Systems, Guest Associate Editor, December 2019--December 2021.
  • Concurrency and Computation Practice and Experience (CCPE) special issue on CANDAR 2020, Guest Editor, 2021.
  • International Journal of Networking and Computing (IJNC) special issue on CANDAR 2020, Guest Editor, 2021.
  • 電子情報通信学会中国支部 フレッシュITあわ〜ど2021, 外部審査員, October 2021.
  • Concurrency and Computation Practice and Experience (CCPE) special issue on CANDAR 2019, Guest Editor, 2020.
  • Special Section on Parallel and Distributed Computing and Networking of IEICE Transactions on Information and Systems, Guest Associate Editor, December 2015--December 2019.
  • Concurrency and Computation Practice and Experience (CCPE) special issue on CANDAR 2018, Guest Editor, 2019.
  • 2020年電子情報通信学会総合大会 実行委員会 委員, 2019--2020.
  • International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), Program Committee, 2017--2019.
  • The 9th International Workshop on Networking, Computing, Systems, and Software (NCSS-9), Program Committee, 2019.
  • 電子情報通信学会コンピュータシステム研究会専門委員会 幹事補佐, May 2017--May 2019.
  • International Journal of Networking and Computing (IJNC), Guest Editor, 2017--2018.
  • 電子情報通信学会リコンフィギャラブルシステム研究会専門委員会 専門委員, May 2012--May 2018.
  • 電子情報通信学会中国支部 フレッシュITあわ〜ど2020, 外部審査員, October 2020.
  • 電子情報通信学会中国支部 フレッシュITあわ〜ど2019, 外部審査員, October 2019.
  • 電子情報通信学会中国支部 フレッシュITあわ〜ど2018, 外部審査員, October 2018.
  • 電子情報通信学会中国支部 学生ケータイあわ〜ど2017, 外部審査員, October 2017.
  • International Journal of Networking and Computing (IJNC), Secretariat, 2010--2017.
  • 電子情報通信学会コンピュータシステム 研究会専門委員会 専門委員, May 2016--May 2017.
  • 電子情報通信学会中国支部 学生会顧問 兼 運営委員, June 2015--May 2017.
  • 平成28年度 電気・情報関連学会中国支部第67回連合大会 実行委員会 委員
  • International Journal of Networking and Computing (IJNC), Guest Editor, 2014.
  • LAシンポジウム2014 事務局
  • 情報処理学会中国支部 幹事, 2012--2014.
  • Special Issue of International Journal of Networking and Computing on Selected Papers from International Conference Networking and Computing (IJNC), Guest Editor, 2011--2013.
  • Special Section on Circuit System and Computer Technologies of IEICE Trans. Fundamentals, Guest Associate Editor, 2012--2013.
  • International Conference on Networking and Computing (ICNC), Registration and Finance Chair, 2011--2012.
  • International Workshop on Networking, Computing, Systems, and Software (NCSS), Program co-chair, 2011--2012.
  • 平成22～25年度 電気・情報関連学会中国支部連合大会 大会委員会 委員
  • 平成23・24年度 電子情報通信学会 会誌編集委員会 委員
  • 平成24年度 電子情報通信学会 代議員
  • International Workshop on Advances in Networking and Computing (WANC), Program Committee, 2011.
  • International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), Program co-chair, 2009--2011.
  • 平成22・23年度 電子情報通信学会中国支部 庶務幹事
  • 平成23年度電子情報通信学会 互選代議員
  • International Conference on Networking and Computing (ICNC), Local Arrangement and Finance Chair, 2010.
  • International Workshop on Advances in Networking and Computing (WANC), Program co-chair, 2010.
  • International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), Local Arrangement Chair, 2009.
  • International Symposium on Parallel and Distributed Processing with Applications (ISPA), Program Committee, 2009.
  • 平成19年度 電気・情報関連学会中国支部第58回連合大会 実行委員会 委員
  • LAシンポジウム2006 事務局.

連絡先

  • E-mail: yasuaki@cs.hiroshima-u.ac.jp
  • 〒739-8527 東広島市鏡山1-4-1 広島大学大学院先進理工系科学研究科情報科学プログラム
  • TEL&FAX: 082-424-7681 (直通)