国内学会(査読なし) (Domestic Conferences (Non-refereed))

  1. 林川雅俊, 中野浩嗣, 伊藤靖朗, 安戸僚汰, ブルームフィルタを用いたGPU上の高速パターンテスト, Proc. of the 15th Workshop on Theoretical Computer Science, pp. 1-12, Takehara, Hiroshima, September 2019.
  2. 吹田駿介, 西村崇宏, 戸倉宏樹, 中野浩嗣, 伊藤靖朗, 笠置明彦, 田原司睦, Convolution-PoolingのGPUへの効率良い実装方法, Proc. of the 15th Workshop on Theoretical Computer Science, pp. 13-21, Takehara, Hiroshima, September 2019.
  3. Shunji Funasaka, Koji Nakano, Yasuaki Ito, Single Kernel Soft Synchronization Technique for Task Arrays on CUDA-enabled GPUs, with Applications, Proc. of the 14th Workshop on Theoretical Computer Science, pp. 109--131, Iizuka, Fukuoka, September 2018.
  4. 松村 直樹，戸倉 宏樹，黒田 悠希，伊藤 靖朗，中野 浩嗣, GPU を⽤いたタイルアート⽣成の２つの⽅法, Proc. of the 14th Workshop on Theoretical Computer Science, pp. 132--150, Iizuka, Fukuoka, September 2018.
  5. 和田 啄茉, 松村 直樹, 中野 浩嗣, 伊藤 靖朗, FPGA へのブルームフィルタの効率よい実装法, Proc. of the 14th Workshop on Theoretical Computer Science, pp. 158--174, Iizuka, Fukuoka, September 2018.
  6. 小森 亮太, 伊藤 靖朗, 中野 浩嗣, １万円ゲームの最強戦略, Proc. of the 14th Workshop on Theoretical Computer Science, pp. 181--194, Iizuka, Fukuoka, September 2018. (優秀研究賞)
  7. 松村 直樹，戸倉 宏樹，黒田 悠希，伊藤 靖朗，中野 浩嗣, 局所探索と機械学習を用いたタイルアート画像生成手法, Technical Report of IPSJ, Vol. 2018-AL-169, No. 4, Otaru, Hokkaido, September 2018.
  8. 佐伯 和人，伊藤 靖朗，中野 浩嗣, FPGAを用いたコラッツ予想の網羅的検証の高速化, Technical Report of IPSJ, Vol. 2018-AL-169, No. 5, Otaru, Hokkaido, September 2018.
  9. 船坂峻慈, 中野浩嗣, 伊藤靖朗, 単一カーネル同期テクニックを用いたGPUアプリケーション, IEICE Technical Report, Vol. 117, No. 314, IEICE-CPSY2017-56, pp. 33--38, Aomori, Aomori, November 2017.
  10. 戸倉宏樹, 黒田悠希, 伊藤靖朗, 中野浩嗣, 正方形点描画像生成のGPU実装, IEICE Technical Report, Vol. 117, No. 314, IEICE-CPSY2017-57, pp. 39--44, Aomori, Aomori, November 2017.
  11. 和田啄茉, 船坂峻慈, 中野浩嗣, 伊藤靖朗, 近似文字列マッチングのハイブリッドアーキテクチャとそのFPGA実装, IEICE Technical Report, Vol. 117, No. 314, IEICE-CPSY2017-57, pp. 45--58, Aomori, Aomori, November 2017.
  12. 本田啓朗, 本田巧, 山元晨之介, 中野浩嗣, 伊藤靖朗, ボロノイ図とユークリッド距離マップ計算のGPU実装, IEICE Technical Report, Vol. 117, No. 153, IEICE-CPSY2017-18, pp. 13--18, Akita, Akita, July 2017.
  13. 柄本悠太郎, 本田巧, 中野浩嗣, 伊藤靖朗, Summed Area Table計算の効率的なGPU実装, IEICE Technical Report, Vol. 117, No. 153, IEICE-CPSY2017-19, pp. 19--24, Akita, Akita, July 2017.
  14. Kohei Yamashita, Yasuaki Ito, Koji Nakano, Bulk Execution of the Dynamic Programming for the Optimal Polygon Triangulation on the GPU, IEICE Technical Report, Vol. 117, No. 28, IEICE-COMP2017-3, pp. 17--22, Nagasaki, Nagasaki, May 2017.
  15. Takahiro Nishimura, Jacir L. Bordim, Yasuaki Ito, Koji Nakano, A GPU Implementation of the Smith-Waterman Algorithm using Bitwise Parallel Bulk Computation Technique, IEICE Technical Report, Vol. 117, No. 28, IEICE-COMP2017-4, pp. 23--30, Nagasaki, Nagasaki, May 2017.
  16. Hiroki Tokura, Takumi Honda, Yasuaki Ito, Koji Nakano, Mitsuya Nishino, Yushiro Hirota, Masami Saeki, A GPU Implementation of Eigenvalue Computation for a Large Number of Matrices, IEICE Technical Report, Vol. 116, No. 240, IEICE-CPSY2016-45, pp. 13--18, Chiba, Chiba, October 2016.
  17. Shunji Funasaka, Koji Nakano, Yasuaki Ito, A Loss-Less Data Compression Algorithm for GPUs, IEICE Technical Report, Vol. 116, No. 240, IEICE-CPSY2016-46, pp. 19--24, Chiba, Chiba, October 2016.
  18. Xin Zhou, Yasuaki Ito, Koji Nakano, An FPGA Implementation of LZW Compression, IEICE Technical Report, Vol. 116, No. 177, IEICE-CPSY2016-11, pp. 7--12, Matsumoto, Nagano, August 2016.
  19. Toru Fujita, Koji Nakano and Yasuaki Ito, A GPU Implementation of the CKY Parsing using Bitwise Parallel Bulk Computation , IEICE Technical Report, Vol. 116, No. 177, IEICE-CPSY2016-12, pp. 13--18, Matsumoto, Nagano, August 2016.
  20. 松本 直之, 周 昕, 中野 浩嗣, 伊藤 靖朗, FPGAを用いたハードウェアソーティングアルゴリズムの実装, IEICE Technical Report, Vol. 115, No. 447, IEICE-ICD2015-103, pp. 37--42, Higashi-Hiroshima, Hiroshima, March 2016.
  21. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of LZW Decompression on the FPGA, IEICE Technical Report, Vol. 115, No. 447, IEICE-ICD2015-104, pp. 43--48, Higashi-Hiroshima, Hiroshima, March 2016.
  22. Takumi Honda, Yasuaki Ito, Koji Nakano, A Warp-synchronous Implementation for Multiple-length Multiplication on the GPU, Proc. of The 11th Workshop on Theoretical Computer Science, pp. 100--106, Kita-Nagoya, Aichi, September 2015.
  23. Toru Fujita, Daigo Nishikori, Koji Nakano and Yasuaki Ito, Efficient GPU implementations for the Conway’s Game of Life, Proc. of The 11th Workshop on Theoretical Computer Science, pp. 169--178, Kita-Nagoya, Aichi, September 2015.
  24. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, A Parallel Algorithm for LZW decompression, with GPU implementation, Proc. of The 11th Workshop on Theoretical Computer Science, pp. 179--188, Kita-Nagoya, Aichi, September 2015.
  25. 本田 巧, 伊藤 靖朗, 中野 浩嗣, GPU向け多倍長整数乗算, IEICE Technical Report, Vol. 115, No. 174, CPSY2015-22, pp. 79--84, Beppu, Oita, August 2015.
  26. Shunji Funasaka, Yasuaki Ito, Koji Nakano, A Parallel Algorithm for LZW decompression, with GPU implementation, IEICE Technical Report, Vol. 115, No. 174, CPSY2015-24, pp. 91--96, Beppu, Oita, August 2015.
  27. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Implementations of Parallel Error Diffusion Optimized for GPU, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-57, pp. 19--24, Higashihiroshima, Hiroshima, November 2014.
  28. Daisuke Takafuji, Yasuaki Ito, and Koji Nakano, C2CU: A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-67, pp. 75--80, Higashihiroshima, Hiroshima, November 2014.
  29. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Verification of the Collatz Conjecture, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-68, pp. 81--86, Higashihiroshima, Hiroshima, November 2014.
  30. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, A GPU Implementation of Clipping-Free Halftoning using the Direct Binary Search, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-69, pp. 87--92, Higashihiroshima, Hiroshima, November 2014.
  31. 谷 和也, 中野 浩嗣, 伊藤 靖朗, GPUを用いた高スループット計算システムの実装, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-70, pp. 93--98, Higashihiroshima, Hiroshima, November 2014.
  32. 酒井 亮輔, 中野 浩嗣, 伊藤 靖朗, GPUを用いたRSA暗号の高速化, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-71, pp. 99--104, Higashihiroshima, Hiroshima, November 2014.
  33. Xin Zhou, Yasuaki Ito, and Koji Nakano,　An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA, IEICE Technical Report, Vol. 114, No. 155, CPSY2014-12, pp. 13--18, Niigata, Niigata, July 2014.
  34. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, IEICE Technical Report, Vol. 114, No. 155, CPSY2014-23, pp. 79--84, Niigata, Niigata, July 2014.
  35. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  36. Xin Zhou, Yasuaki Ito, and Koji Nakano, An Efficient Implementation of the Gradient-Based Hough Transform Using DSP Blocks and Block RAMs on the FPGA, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  37. Daisuke Takafuji, Yasuaki Ito, and Koji Nakano, C2CU: A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  38. Koji Nakano, Susumu Matsumae, and Yasuaki Ito, Random Address Permute-Shift Technique for the Shared Memory on GPUs, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  39. 高下 孔明, 伊藤 靖朗, 中野 浩嗣, GPUを用いたClipping-free Direct Binary Searchの高速化, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  40. 本田 巧, 伊藤 靖朗, 中野 浩嗣, GPUを用いたコラッツ予想検証の高速化, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  41. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano, and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, IEICE Technical Report, Vol. 113, No. 324, CPSY2013-69, pp. 59--64, Kagoshima, Kagoshima, November 2013.
  42. Ryoshuke Nakamura and Yasuaki Ito and Koji Nakano, TinyCSE: Tiny Computer System for Education, IEICE Technical Report, Vol. 113, No. 324, CPSY2013-66, pp. 41--45, Kagoshima, Kagoshima, November 2013.
  43. Manduhu, Koji Nakano, and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, IEICE Technical Report, Vol. 113, No. 282, CPSY2013-41, pp. 13--18, Higashihiroshima, Hiroshima, November 2013.
  44. 蓬郷 典大, 中野 浩嗣, 伊藤 靖朗, GPUを用いたハフ変換の実装, IEICE Technical Report, Vol. 113, No. 282, CPSY2013-42, pp. 19--24, Higashihiroshima, Hiroshima, November 2013.
  45. Duhu Man, Koji Nakano, and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 15--20, Karatsu, Saga, September 2013.
  46. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano, and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, with Performance Evaluation, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 21--30, Karatsu, Saga, September 2013.
  47. Koji Nakano, Susumu Matsumae, and Yasuaki Ito, The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 83--91, Karatsu, Saga, September 2013.
  48. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 92--101, Karatsu, Saga, September 2013.
  49. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito, Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 102--108, Karatsu, Saga, September 2013.
  50. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito, and Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, IEICE Technical Report, Vol. 113, No. 169, CPSY2013-15, pp. 31--35, Kitakyushu, Fukuoka, August 2013.
  51. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, Vol. 113, No. 169, CPSY2013-16, pp. 37--42, Kitakyushu, Fukuoka, August 2013.
  52. Kaoru Hashimoto, Yasuaki Ito, Koji Nakano, Template Matching using DSP slices on the FPGA, Vol. 113, No. 169, CPSY2013-17, pp. 43--48, Kitakyushu, Fukuoka, August 2013.
  53. Xin Zhou, Yasuaki Ito, and Koji Nakano, An implementation of Hough Transform Using DSP blocks and block RAMs on the FPGA, IEICE Technical Report, Vol. 112, No. 237, CPSY2012-31, pp. 1--6, Higashihiroshima, Hiroshima, October 2012.
  54. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, A GPU Implementation of Conflict-Free Offline Permutation, IEICE Technical Report, Vol. 112, No. 237, CPSY2012-35, pp. 25--30, Higashihiroshima, Hiroshima, October 2012.
  55. Akihiro Uchida, Yasuaki Ito, Koji Nakano, An Efficient Implementation of Ant Colony Optimization for the Traveling Salesman Problem on the GPU, IEICE Technical Report, Vol. 112, No. 237, CPSY2012-36, pp. 31--36, Higashihiroshima, Hiroshima, October 2012.
  56. Xin Zhou, Yasuaki Ito, and Koji Nakano, Fast Hough Transform Using DSP blocks and block RAMs on the FPGA, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 27--33, Kobe, Hyogo, September 2012.
  57. Kazufumi Nishida, Koji Nakano, and Yasuaki Ito, Accelerating Dynamic Programming for the Optimal Polygon Triangulation on the GPU, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 34--41, Kobe, Hyogo, September 2012.
  58. Akihiro Uchida, Yasuaki Ito, Koji Nakano, An Efficient GPU Implementation of Ant Colony Optimization for the Traveling Salesman Problem, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 42--50, Kobe, Hyogo, September 2012.
  59. Duhu Man, Kenji Uda, Yasuaki Ito and Koji Nakano, Accelerating Computation of Euclidean Distance Map using the GPU with Efficient Memory Access, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 51--63, Kobe, Hyogo, September 2012.
  60. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Implementation of Data Permutation on the GPU, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 113--119, Kobe, Hyogo, September 2012.
  61. Yuki Agou, Yasuaki Ito, Koji Nakano, An FPGA Implementation for a 3-layer Perceptron with the FDFM Processor Core Approach, IEICE Technical Report, Vol. 112, No. 70, RECONF2012-8, pp. 43--48, Naha, Okinawa, May 2012.
  62. Yasuaki Ito, Koji Nakano, and Bo Song, The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption, Proc. of The 7th Workshop on Theoretical Computer Science, pp. 103--113, Fukuma, Fukuoka, September 2011.
  63. Yuki Ago, Atsuo Inoue, Koji Nakano, Yasuaki Ito, The Parallel FDFM Processor Core Approach for Neural Networks, Proc. of The 7th Workshop on Theoretical Computer Science, pp. 114--120, Fukuma, Fukuoka, September 2011.
  64. Akihiro Uchida, Yasuaki Ito, and Koji Nakano, Fast and Accurate Template Matching using Pixel Rearrangement on the GPU, Proc. of The 7th Workshop on Theoretical Computer Science, pp. 167--172, Fukuma, Fukuoka, September 2011.
  65. 伊藤靖朗, 中野浩嗣, FPGA のDSP ブロックを用いた高速計算, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 70--75, Nagashima, Mie, September 2010.
  66. Bo Song, Kensuke Kawakami, Koji Nakano and Yasuaki Ito, An RSA Encryption using DSP slices and Block RAMs on the FPGA, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 76--84, Nagashima, Mie, September 2010.
  67. Md. Nazrul Islam Mondal, Koji Nakano and Yasuaki Ito, An Algorithm to Remove Asynchronous ROMs, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 85--92, Nagashima, Mie, September 2010.
  68. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito and Koji Nakano, Implementations of Parallel Euclidean Distance Map Computation in Multicore Processors and GPUs, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 93--100, Nagashima, Mie, September 2010.
  69. Yasuaki Ito and Koji Nakano, An Effcient Implementation of Exaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs, IEICE Technical Report, Vol. 110, No. 32, RECONF2010-15, pp. 69--74, Nagasaki, May 2010.
  70. Yasuaki Ito and Koji Nakano, Component Labeling on the FPGA using Few Logic Elements, IEICE Technical Report, Vol. 109, No. 198, RECONF2009-20, pp. 7--12, Utsunomiya, September 2009.
  71. Koji Nakano, Yasuaki Ito, Kensuke Kawakami, Koji Shigemoto, An FPGA-based Tiny Processing System for Small Embedded System and Education, IEICE Technical Report, Vol. 109, No. 198, RECONF2009-32, pp. 79--84, Utsunomiya, September 2009.
  72. Yasuaki Ito and Koji Nakano, An FPGA-based Architecture for Verifying Collatz Conjecture, IEICE Technical Report, Vol. 109, No. 198, RECONF2009-40, pp. 125--130, Utsunomiya, September 2009.
  73. Yasuaki Ito and Koji Nakano, A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Conjecture, Proc. of The 5th Workshop on Theoretical Computer Sciences, pp.7--14, Hiroshima, September 2009.
  74. 中河雅弥，伊藤靖朗，中野浩嗣, 並列凸包計算アルゴリズムのマルチコアプロセッサ上での評価, Proc. of The 5th Workshop on Theoretical Computer Science, pp. 67--68, Hiroshima, September 2009.
  75. Duhu Man , Yasuaki Ito and Koji Nakano, Parallel Sampling Sorting on the Multicore Processors, Proc. of The 5th Workshop on Theoretical Computer Science, pp. 69--70, Hiroshima, September 2009.
  76. 伊藤靖朗, 同期ブロックRAMの非同期ブロックRAMへの変換について, Proc. of The 4th Workshop on Theoretical Computer Sciences, pp.151--157, Nagahama, Shiga, September 2008.
  77. Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, and Yasuaki Ito, A Tiny Processing System for Education and Small Embedded System on the FPGA, Proc. of The 4th Workshop on Theoretical Computer Sciences, pp.135--142, Nagahama, Shiga, September 2008.
  78. Yasuaki Ito and Koji Nakano, Component Labeling for k-Concave Binary Images Using an FPGA, IEICE Technical Report, Vol. 107, No. 390, COMP2007-48, pp. 1--8, Hiroshima, December 2007.
  79. 伊藤靖朗, 中野浩嗣, FPGAを用いた二値画像のラベリング, Proc. of The 3rd Workshop on Theoretical Computer Sciences, pp.6--12, Mojiko, Fukuoka, September 2007.
  80. 伊藤 靖朗, 中野 浩嗣，山岸 洋平, n Choose k カウンタのハードウェア実装とその応用, Proc. of The 2nd Workshop on Theoretical Computer Sciences, pp.68--69, Seto, Aichi,September 2006.
  81. 伊藤 靖朗, 中野 浩嗣, FPGAを用いた相関係数による画像のパターンマッチング,　2006年度 夏のLAシンポジウム, Hiroshima, August 2006.
  82. 伊藤 靖朗, 中野 浩嗣, FPGAを用いた大きな文法のCKYパージング, 平成16年度電気・情報関連学会中国支部第55回連合大会講演論文集, p.308, Ube, Yamaguchi, September 2004.
  83. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Instance-Specific Solutions for the CKY Parsing, 第１回 リコンフィギャラブル研究会 論文集, pp.27-33, Kumamoto, September 2003.
  84. Y. Ito, J. L. Bordim, and K. Nakano, Accelerating the CKY Parsing using FPGAs, Technical Report of IPSJ, AL2002-85 , pp. 35-42, Tokyo, July 2002.